Patents by Inventor Kenji Sugiura

Kenji Sugiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200273847
    Abstract: An LED support for at least two groups R, G, B, M of semiconductor light sources r, g, b, m connected in series is provided with conductor tracks which allow series connections of the semiconductor light sources of each of the groups. Said series connections together with connected voltage or current sources form independent loops which are arranged on the LED support in a non-planar line pattern. This allows the arrangement of the semiconductor light sources on rings which are concentric to one another, wherein at least two of said rings contain semiconductor light sources which belong to at least two of the different groups. A constant brightness and light distribution is achieved over the surface of the LED light source. Necessary line bridges are formed by bonded wire bridges which directly adjoin the LED chips and bridge a line leading to a chip bonding surface.
    Type: Application
    Filed: August 7, 2018
    Publication date: August 27, 2020
    Inventor: Kenji Sugiura
  • Publication number: 20200235123
    Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 23, 2020
    Inventors: Kenji SUGIURA, Mitsuteru MUSHIGA, Yuji FUKANO, Akio NISHIDA
  • Publication number: 20200219896
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.
    Type: Application
    Filed: January 7, 2019
    Publication date: July 9, 2020
    Inventors: Mitsuteru MUSHIGA, Kenji SUGIURA, Akio NISHIDA
  • Publication number: 20200219895
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.
    Type: Application
    Filed: January 7, 2019
    Publication date: July 9, 2020
    Inventors: Mitsuteru MUSHIGA, Kenji SUGIURA, Akio NISHIDA, Ryosuke KANEKO, Michiaki SANO
  • Publication number: 20200182321
    Abstract: A friction material for dry brakes containing, as raw friction materials, a fiber substrate, a binder, an organic filler, and an inorganic filler, wherein porous silica including a plurality of pores with a central pore diameter of 1.0 nm or greater and 50.0 nm or smaller that absorbs liquid matter generated by thermal decomposition of an organic matter in the friction material at the time of brake braking is contained as the inorganic filler.
    Type: Application
    Filed: July 23, 2018
    Publication date: June 11, 2020
    Applicant: ADVICS CO., LTD.
    Inventors: Junichi UJITA, Manami SUGIRA, Katsuya OKYAMA, Takatoshi TAKEMOTO, Kenji ABE, Toru MATSUSHIMA, Mamoru TOYAMA, Yuji NAGASAWA, Nnvoru SUGIURA
  • Patent number: 10677287
    Abstract: A bearing structure S includes: a bearing hole formed in a housing; a main body portion of a bearing provided in the bearing hole and inserted with a shaft therethrough; damper surface and provided on an outer circumferential surface of the main body portion, the damper surface facing an inner circumferential surface of the bearing hole; thrust surface provided at end portions of the main body portion in an axial direction of the shaft; and thrust back surface portions provided in the main body portion and having an outer diameter larger than those of the damper surface, the thrust back surface portions spaced apart from the damper surface by a distance farther than a distance between each of the damper surface and the inner circumferential surface of the bearing hole and positioned on back sides of the thrust surface.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: June 9, 2020
    Assignee: IHI Corporation
    Inventors: Yutaka Uneura, Shinichi Kaneda, Shunsuke Nishii, Hideyuki Kojima, Tomomi Sugiura, Kenji Bunno
  • Patent number: 10669891
    Abstract: A bearing structure includes: a housing; a bearing hole, which is formed in the housing, and receives a bearing configured to axially support a shaft having one end provided with an impeller; a clearance groove, which is formed in an inner circumferential surface of the bearing hole, and communicates with a passage formed on a lower side of the shaft; and an inclined portion formed on an inner wall surface of the clearance groove, which is positioned at least above the shaft.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 2, 2020
    Assignee: IHI Corporation
    Inventors: Kenji Bunno, Yutaka Uneura, Shinichi Kaneda, Yuichi Daito, Hideyuki Kojima, Tomomi Sugiura, Shunsuke Nishii
  • Patent number: 10665607
    Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 26, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kenji Sugiura, Mitsuteru Mushiga, Yuji Fukano, Akio Nishida
  • Patent number: 10629611
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Kiyohiko Sakakibara, Mitsuteru Mushiga, Hisakazu Otoi, Kenji Sugiura
  • Patent number: 10610928
    Abstract: A powder for a conductive material according to an embodiment of the present invention includes a large number of particles that contain copper as a main component and having an average primary particle diameter of 1 nm or more and 200 nm or less. The particles contain titanium on surfaces or inside thereof, and a content of the titanium is 0.003 atomic percent or more and 0.5 atomic percent or less.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: April 7, 2020
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Issei Okada, Motohiko Sugiura, Yoshio Oka, Kenji Ohki
  • Patent number: 10586803
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 10, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mitsuteru Mushiga, Hisakazu Otoi, Kenji Sugiura, Zhixin Cui, Kiyohiko Sakakibara
  • Patent number: 10540695
    Abstract: There is provided an information providing device which, even when one advertisement display area is shared between a plurality of advertisers, can increase the probability that, for example, a banner advertisement of each advertiser is specified and efficiently display information matching each advertiser. The information providing device is configured to, when a user of a terminal device specifies an advertisement display area, specify a partial area including a position specified in the advertisement display area, and transmit information matching a provider allocated to the partial area to the terminal device.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: January 21, 2020
    Assignee: Rakuten, Inc.
    Inventors: Kenji Sugiura, Yasuaki Shirogane
  • Publication number: 20200010580
    Abstract: A disclosed three-dimensional modeling composition set includes a first composition, and a second composition, where at least one of a cured product of the first composition and a cured product of the second composition has water disintegratability, and when ST1 represents surface tension of the first composition and ST2 represents surface tension of the second composition, the following formula (1) is satisfied: IST1?ST2I?2 (1) where in the formula (1), the unit of the surface tension is mN/m. A method and an apparatus using the three-dimensional modeling composition set are also disclosed.
    Type: Application
    Filed: March 23, 2018
    Publication date: January 9, 2020
    Applicant: Ricoh Company, Ltd.
    Inventors: Yoshihito SHIMADA, Yoshihiro NORIKANE, Kenji SUGIURA, Hiroyuki NAITO
  • Patent number: 10490564
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: November 26, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mitsuteru Mushiga, Hisakazu Otoi, Kenji Sugiura
  • Patent number: 10480575
    Abstract: A bearing structure includes: a housing; a bearing hole formed in the housing and provided with a bearing for pivotally supporting a shaft; a clearance groove provided in the bearing hole, having an opposing wall portion radially opposed to the shaft, and communicating with an oil drainage passage provided below a shaft center of the shaft; and at least one of a narrow portion or a wide portion in the opposing wall portion of the clearance groove with a boundary right above the shaft center of the shaft, the narrow portion provided in a rear side in a rotation direction of the shaft, the narrow portion having a narrower gap from the shaft than that in a front side in the rotation direction of the shaft, the wide portion provided in the front side in the rotation direction of the shaft, the wide portion having a wider gap from the shaft than that in the rear side in the rotation direction of the shaft.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: November 19, 2019
    Assignee: IHI Corporation
    Inventors: Kenji Bunno, Yutaka Uneura, Shinichi Kaneda, Yuichi Daito, Hideyuki Kojima, Tomomi Sugiura, Shunsuke Nishii
  • Publication number: 20190326313
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 24, 2019
    Inventors: Zhixin Cui, Kiyohiko Sakakibara, Mitsuteru Mushiga, Hisakazu Otoi, Kenji Sugiura
  • Publication number: 20190326307
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 24, 2019
    Inventors: Mitsuteru Mushiga, Hisakazu Otoi, Kenji Sugiura
  • Publication number: 20190326306
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 24, 2019
    Inventors: Mitsuteru Mushiga, Hisakazu Otoi, Kenji Sugiura, Zhixin Cui, Kiyohiko Sakakibara
  • Patent number: 10393170
    Abstract: A bearing structure includes: a housing; a bearing hole formed in the housing; a bearing, which is provided in the bearing hole, and is configured to axially support a shaft having one end provided with a turbine impeller; a space, which is formed in the housing, and is positioned between the impeller and the bearing hole; a passage, which communicates with the space, and extends to a vertically lower side of the bearing hole; a communication opening portion, which allows the passage and the bearing hole to communicate with each other; and a lower wall portion, which is provided in a lower portion including a portion directly below an axis of the shaft between the passage and the bearing hole, and has an inner wall surface being opposed to the shaft and having a curved surface shape with a curvature center positioned on the shaft side.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: August 27, 2019
    Assignee: IHI Corporation
    Inventors: Kenji Bunno, Yutaka Uneura, Shinichi Kaneda, Yuichi Daito, Hideyuki Kojima, Tomomi Sugiura, Shunsuke Nishii
  • Patent number: RE47780
    Abstract: A light-emitting apparatus according to the present invention includes: an elongated substrate; a plurality of LEDs arranged in a straight line on the substrate in a longitudinal direction of the substrate; and a sealing member that includes an optical wavelength converter and seals the LEDs, wherein the sealing member is formed in a straight line in a direction of arrangement of the LEDs and seals the LEDs collectively.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: December 24, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Kenji Sugiura