Patents by Inventor Kenji Sugiura

Kenji Sugiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240307967
    Abstract: A three-dimensional object fabrication apparatus includes a fabrication unit that fabricates a fabricated object containing metal powder; a recovering unit that recovers at least a part of the powder as recovered powder; a powder mixer that generates mixed powder containing at least the recovered powder; and a controller that controls a mixing ratio of new powder of the powder and the recovered powder based on information on at least one state of the powder, the recovered powder, or the mixed powder.
    Type: Application
    Filed: March 6, 2024
    Publication date: September 19, 2024
    Inventors: Yasuaki YOROZU, Kenji SUGIURA
  • Publication number: 20240300021
    Abstract: A drying device includes a housing section and a drying section. The housing section is configured to house a powder bound object. The drying section is configured to dry the powder bound object housed in the housing section. The housing section includes a bottom. The bottom includes a periphery. The bottom includes an air vent inside of the periphery.
    Type: Application
    Filed: March 7, 2024
    Publication date: September 12, 2024
    Inventors: Kenichiroh HASHIMOTO, Kenji SUGIURA, Toshiyuki MUTOH
  • Publication number: 20240196610
    Abstract: A memory device is formed by forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming memory openings through the alternating stack, forming memory opening fill structures in the memory openings, forming an access trench through a portion of the alternating stack forming an access trench fill structure in the access cavity, and iteratively performing multiple instances of a unit processing sequence. Each instance of the unit processing sequence includes a vertical recess etch step that vertically recesses the access trench fill structure and an isotropic etch step that isotropically recesses the sacrificial material layers. A finned access cavity is formed after the multiple instances of the unit processing sequence. A finned dielectric support structure is formed in the finned access cavity, and the sacrificial material layers are replaced with electrically conductive layers.
    Type: Application
    Filed: July 11, 2023
    Publication date: June 13, 2024
    Inventors: Ryoichi EHARA, Kenji SUGIURA, Katsufumi OKAMOTO, Yudai TANAKA, Kota FUNAYAMA
  • Publication number: 20240173776
    Abstract: A three-dimensional fabrication apparatus includes a fabrication section, a liquid discharge unit, a housing, and a gas replacer. The fabrication section forms a powder layer with a fabrication material in a fabrication area. The liquid discharge unit discharges a fabrication liquid onto the powder layer to form a fabrication layer. The housing has an internal space accommodating at least one of the fabrication section or the liquid discharge unit. The gas replacer to generate and supply a laminar flow of a predetermined gas other than an air into the internal space of the housing to replace an ambient gas in the internal space from the air to the predetermined gas.
    Type: Application
    Filed: November 22, 2023
    Publication date: May 30, 2024
    Applicant: Ricoh Company, Ltd.
    Inventors: Kenji Sugiura, Hiromitsu Ishii
  • Patent number: 11521244
    Abstract: An information providing device acquires a keyword specified from a page on which an advertisement display area used for displaying an advertisement is arranged, selects advertisements corresponding to the keyword from a storing means storing information of each of a plurality of advertisements as display target candidates, and specifies a display target advertisement to be displayed in the advertisement display area of the page from among the display target candidates. Then, the information providing device, in a case where the display target candidate that is not specified among the display target candidates of a same advertiser as that of the specified display target advertisement satisfies a predetermined condition, determines the display target candidate and the display target advertisement as display target advertisements to be displayed in the advertisement display area.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: December 6, 2022
    Assignee: Rakuten Group, Inc.
    Inventor: Kenji Sugiura
  • Patent number: 11078374
    Abstract: Provided is an active-energy-ray-curable liquid composition containing a monomer (A) having a hydrogen-bonding capacity and a solvent (B) having a hydrogen-bonding capacity, wherein the active-energy-ray-curable liquid composition satisfies conditions below, <Conditions> a cured product obtained by irradiating the active-energy-ray-curable liquid composition with 500 mJ/cm2 of an active energy ray is a solid having a compressive stress of 2.0 kPa or greater when compressed by 1% at 25 degrees C., and the cured product has a water decaying property.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: August 3, 2021
    Assignee: RICOH COMPANY, LTD.
    Inventors: Hiroyuki Naito, Hiroshi Iwata, Yoshihiro Norikane, Yoshihito Shimada, Kenji Sugiura
  • Patent number: 10923496
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: February 16, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mitsuteru Mushiga, Kenji Sugiura, Akio Nishida, Ryosuke Kaneko, Michiaki Sano
  • Patent number: 10892267
    Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-protruding portion of the contact via structure contacts an annular top surface of the electrically conductive layer. The electrical isolation can be provided by a ribbed insulating spacer that includes laterally-protruding annular rib regions at levels of the insulating layers, or can be provided by annular insulating spacers located at levels of the electrically conductive layers. The contact via structure can contact a top surface of an underlying metal interconnect structure that overlies a substrate to provide an electrically conductive path.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: January 12, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mitsuteru Mushiga, Kenji Sugiura, Hisakazu Otoi, Shigehisa Inoue, Yuki Fukuda
  • Patent number: 10848082
    Abstract: The present disclosure provides a driving device with a low cost and/or a simple advance angle control for a motor. A voltage zero crossing detecting unit 314 is configured to detect an induced voltage generated from a coil with a specific phase of a fan motor 202 being zero of a voltage zero crossing point. A detection period setting unit 316 is configured to set at least one detection period synchronously with the voltage zero crossing point. A coil voltage detection comparator 302 is configured to compare a terminal voltage generated from one end of the coil with the specific phase with a threshold voltage, and generate a coil voltage detection signal S3 indicating a comparison result. A current phase detecting unit 318 is configured to generate a phase detection signal S8 indicating a relationship between the coil current flowing through the coil with the specific phase and a phase of an induced voltage based on a level of the coil voltage detection signal S3 in the detection period.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: November 24, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Kenji Sugiura
  • Patent number: 10833100
    Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: November 10, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kenji Sugiura, Mitsuteru Mushiga, Yuji Fukano, Akio Nishida
  • Patent number: 10797070
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mitsuteru Mushiga, Kenji Sugiura, Akio Nishida
  • Publication number: 20200273847
    Abstract: An LED support for at least two groups R, G, B, M of semiconductor light sources r, g, b, m connected in series is provided with conductor tracks which allow series connections of the semiconductor light sources of each of the groups. Said series connections together with connected voltage or current sources form independent loops which are arranged on the LED support in a non-planar line pattern. This allows the arrangement of the semiconductor light sources on rings which are concentric to one another, wherein at least two of said rings contain semiconductor light sources which belong to at least two of the different groups. A constant brightness and light distribution is achieved over the surface of the LED light source. Necessary line bridges are formed by bonded wire bridges which directly adjoin the LED chips and bridge a line leading to a chip bonding surface.
    Type: Application
    Filed: August 7, 2018
    Publication date: August 27, 2020
    Inventor: Kenji Sugiura
  • Publication number: 20200235123
    Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 23, 2020
    Inventors: Kenji SUGIURA, Mitsuteru MUSHIGA, Yuji FUKANO, Akio NISHIDA
  • Publication number: 20200219895
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.
    Type: Application
    Filed: January 7, 2019
    Publication date: July 9, 2020
    Inventors: Mitsuteru MUSHIGA, Kenji SUGIURA, Akio NISHIDA, Ryosuke KANEKO, Michiaki SANO
  • Publication number: 20200219896
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.
    Type: Application
    Filed: January 7, 2019
    Publication date: July 9, 2020
    Inventors: Mitsuteru MUSHIGA, Kenji SUGIURA, Akio NISHIDA
  • Patent number: 10665607
    Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 26, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kenji Sugiura, Mitsuteru Mushiga, Yuji Fukano, Akio Nishida
  • Patent number: 10629611
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Kiyohiko Sakakibara, Mitsuteru Mushiga, Hisakazu Otoi, Kenji Sugiura
  • Patent number: 10586803
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 10, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mitsuteru Mushiga, Hisakazu Otoi, Kenji Sugiura, Zhixin Cui, Kiyohiko Sakakibara
  • Patent number: 10540695
    Abstract: There is provided an information providing device which, even when one advertisement display area is shared between a plurality of advertisers, can increase the probability that, for example, a banner advertisement of each advertiser is specified and efficiently display information matching each advertiser. The information providing device is configured to, when a user of a terminal device specifies an advertisement display area, specify a partial area including a position specified in the advertisement display area, and transmit information matching a provider allocated to the partial area to the terminal device.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: January 21, 2020
    Assignee: Rakuten, Inc.
    Inventors: Kenji Sugiura, Yasuaki Shirogane
  • Publication number: 20200010580
    Abstract: A disclosed three-dimensional modeling composition set includes a first composition, and a second composition, where at least one of a cured product of the first composition and a cured product of the second composition has water disintegratability, and when ST1 represents surface tension of the first composition and ST2 represents surface tension of the second composition, the following formula (1) is satisfied: IST1?ST2I?2 (1) where in the formula (1), the unit of the surface tension is mN/m. A method and an apparatus using the three-dimensional modeling composition set are also disclosed.
    Type: Application
    Filed: March 23, 2018
    Publication date: January 9, 2020
    Applicant: Ricoh Company, Ltd.
    Inventors: Yoshihito SHIMADA, Yoshihiro NORIKANE, Kenji SUGIURA, Hiroyuki NAITO