Patents by Inventor Kenji SUINA

Kenji SUINA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Failure detection circuit and semiconductor device
    Patent number: 11639961
    Abstract: A first circuit outputs a third signal having a first level during a period over which first and second signals have the same level, and having a second level during a period over which the first and second signals have different levels. A second circuit outputs a fifth signal having the first level during a period over which a fourth signal having the same level as the third signal has the same level as the first signal, and having the second level during a period over which the first and fourth signals have different levels. A third circuit outputs a sixth signal having a third level during a period over which the second and fifth signals have the same level, and having a fourth level during a period over which the second and fifth signals have different levels.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: May 2, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenji Suina
  • FAILURE DETECTION CIRCUIT AND SEMICONDUCTOR DEVICE
    Publication number: 20210286005
    Abstract: A first circuit outputs a third signal having a first level during a period over which first and second signals have the same level, and having a second level during a period over which the first and second signals have different levels. A second circuit outputs a fifth signal having the first level during a period over which a fourth signal having the same level as the third signal has the same level as the first signal, and having the second level during a period over which the first and fourth signals have different levels. A third circuit outputs a sixth signal having a third level during a period over which the second and fifth signals have the same level, and having a fourth level during a period over which the second and fifth signals have different levels.
    Type: Application
    Filed: September 10, 2020
    Publication date: September 16, 2021
    Inventor: Kenji Suina
  • Node system and supervisory node
    Patent number: 8897289
    Abstract: A node system includes a first node, a second node, and a supervisory node which transmit frames while increasing or decreasing the cycle microtick count, and determines reduced cycle microtick counts by subtracting or adding a rate correction limit value from or to the cycle microtick count of the supervisory node when reception of the first frame transmitted by the first node stop and the cycle microtick count of the supervisory node when reception of the first and second frames stop.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: November 25, 2014
    Assignee: Spansion LLC
    Inventors: Kenji Suina, Takashi Arai, Koichi Mita, Akira Shimamura, Hidetoshi Ishikawa, Takashi Moriya, Yuuki Nozawa, Hideki Kondo
  • Node System and Supervisory Node
    Publication number: 20140286330
    Abstract: A node system includes a first node, a second node, and a supervisory node which transmit frames while increasing or decreasing the cycle microtick count, and determines reduced cycle microtick counts by subtracting or adding a rate correction limit value from or to the cycle microtick count of the supervisory node when reception of the first frame transmitted by the first node stop and the cycle microtick count of the supervisory node when reception of the first and second frames stop.
    Type: Application
    Filed: March 20, 2014
    Publication date: September 25, 2014
    Applicant: Spansion LLC
    Inventors: Kenji Suina, Takashi ARAI, Koichi MITA, Akira SHIMAMURA, Hidetoshi ISHIKAWA, Takashi MORIYA, Yuuki NOZAWA, Hideki KONDO
  • Node system and supervisory node
    Patent number: 8718038
    Abstract: A node system includes a first node, a second node, and a supervisory node which transmit frames while increasing or decreasing the cycle microtick count, and determines reduced cycle microtick counts by subtracting or adding a rate correction limit value from or to the cycle microtick count of the supervisory node when reception of the first frame transmitted by the first node stop and the cycle microtick count of the supervisory node when reception of the first and second frames stop.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: May 6, 2014
    Assignee: Spansion LLC
    Inventors: Kenji Suina, Takashi Arai, Koichi Mita, Akira Shimamura, Hidetoshi Ishikawa, Takashi Moriya, Yuuki Nozawa, Hideki Kondo
  • NODE SYSTEM AND SUPERVISORY NODE
    Publication number: 20120134457
    Abstract: A node system includes a first node, a second node, and a supervisory node which transmit frames while increasing or decreasing the cycle microtick count, and determines reduced cycle microtick counts by subtracting or adding a rate correction limit value from or to the cycle microtick count of the supervisory node when reception of the first frame transmitted by the first node stop and the cycle microtick count of the supervisory node when reception of the first and second frames stop.
    Type: Application
    Filed: August 26, 2011
    Publication date: May 31, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kenji SUINA, Takashi ARAI, Koichi MITA, Akira SHIMAMURA, Hidetoshi ISHIKAWA, Takashi MORIYA, Yuuki NOZAWA, Hideki KONDO