Abstract: A processor includes a first arithmetic device configured to execute a first instruction, and a second arithmetic device configured to execute a second instruction and a third instruction. The first arithmetic device calculates first data by executing the first instruction. The second arithmetic device stops execution of the third instruction based on the second instruction which is an instruction for waiting issuance of first synchronization information, and thereafter executes the third instruction that uses the first data, based on the issuance of the first synchronization information from the first arithmetic device.

Abstract: A data processing device includes an instruction issue circuit configured to issue instructions; a plurality of execution circuits configured to execute, in parallel, the instructions issued from the instruction issue circuit; and a plurality of delay circuits configured to delay arrival timings of when the instructions issued from the instruction issue circuit arrive at the plurality of execution circuits, the plurality of delay circuits being arranged between the instruction issue circuit and the plurality of execution circuits. The arrival timings of the instructions arriving at at least two execution circuits included in the plurality of execution circuits are different from each other.

Abstract: A processor includes an arithmetic circuit configured to execute an arithmetic instruction; and a register configured to hold data used by the arithmetic circuit. The processor receives a data movement instruction and the arithmetic instruction corresponding to the data movement instruction, and moves the data from a first memory to the register based on a data movement instruction. The arithmetic circuit executes the arithmetic instruction after a data movement of the data movement instruction is completed.

Abstract: A multi-core processor has: a plurality of processor cores; and a power management part managing power supplied to the plurality of processor cores. The power management part has a supplied electric energy determination part determining maximum supplied electric energy for each of the plurality of processor cores. The maximum supplied electric energy is an upper limit value of supplied electric energy which can be supplied to the processor core.

Abstract: A multi-core processor has: a plurality of processor cores; and a power management part managing power supplied to the plurality of processor cores. The power management part has a supplied electric energy determination part determining maximum supplied electric energy for each of the plurality of processor cores. The maximum supplied electric energy is an upper limit value of supplied electric energy which can be supplied to the processor core.

Abstract: An information processing device implements a register renaming scheme for managing physical registers (e.g. hardware registers HR) coordinated with logical registers (e.g. software usable registers SUR) in conjunction with a renaming table. A first dedicated instruction is incorporated into an instruction set so that a free physical register is coordinated with a logical register designated by the first dedicated instruction. Alternatively, a second dedicated instruction is incorporated into the instruction set so that a physical register coordinated with a logical register designated by the second dedicated instruction is released to be free. In addition, the optimization is performed to change the number of software usable registers (SUR) and the number of renaming registers (RR) within the physical registers in conformity with the software executing the instruction set. Thus, it is possible to prevent the occurrence of an unwanted memory access instruction and dead time needed for releasing registers.