Abstract: A control method for causing a computer to execute processing of: acquiring supply information indicating supply power supplied to a power grid and grid information indicating a grid capacity of the power grid; determining whether or not the supply power exceeds the grid capacity based on the supply information and the grid information; and if it is determined that the grid capacity is exceeded, performing control so that surplus power exceeding the grid capacity is supplied to a computing device constituting a predetermined distributed computing system.

Abstract: An active region includes a body region in which first and second transistors are formed, a connection portion to which a potential of the body region is connected, and a lead portion that connects the body region and the connection portion. Source regions or drain regions of the first and second transistors formed in the body region are provided in a common region. Each of the lead portions extends from a corresponding channel region such that the lead portions are isolated from each other, and a gate electrode extends thereon. A width of the lead portion is narrower than a distance between corresponding ones of contact portions of the source regions and the drain regions of the first and second transistors. A width of the connection portion is equal to or narrower than a gate width of the gate electrode extending on the lead portion.

Abstract: An active region includes a body region in which first and second transistors are formed, a connection portion to which a potential of the body region is connected, and a lead portion that connects the body region and the connection portion. Source regions or drain regions of the first and second transistors formed in the body region are provided in a common region. Each of the lead portions extends from a corresponding channel region such that the lead portions are isolated from each other, and a gate electrode extends thereon. A width of the lead portion is narrower than a distance between corresponding ones of contact portions of the source regions and the drain regions of the first and second transistors. A width of the connection portion is equal to or narrower than a gate width of the gate electrode extending on the lead portion.

Abstract: A method for fabricating a semiconductor device is provided which has first and second regions, transistors of different conductivity types being formed on parts of a substrate corresponding to the first and second regions. The method includeujs the steps of: (a) forming a first insulating film to cover the parts of the substrate corresponding to the first and second regions; (b) forming a first thin film on the first insulating film, the first thin film having a relatively higher etching rate than the first insulating film in plasma etching using a halogen gas; and (c) removing a part of the first thin film corresponding to the first region by the plasma etching using a mask covering the second region and modifying a part of the first insulating film corresponding to the first region.

Abstract: A method for fabricating a semiconductor device is provided which has first and second regions, transistors of different conductivity types being formed on parts of a substrate corresponding to the first and second regions. The method includes the steps of: (a) forming a first insulating film to cover the parts of the substrate corresponding to the first and second regions; (b) forming a first thin film on the first insulating film, the first thin film having a relatively higher etching rate than the first insulating film in plasma etching using a halogen gas; and (c) removing a part of the first thin film corresponding to the first region by the plasma etching using a mask covering the second region and modifying a part of the first insulating film corresponding to the first region.

Abstract: Variations in the size of a linear pattern resulting from difference in mask pattern layout are prevented by setting the perimeter of the linear pattern per unit area in a specified range irrespective of the type of a semiconductor integrated circuit device or by adjusting a process condition in accordance with type-to-type difference in the perimeter of the linear pattern per unit area.

Abstract: Variations in the size of a linear pattern resulting from difference in mask pattern layout are prevented by setting the perimeter of the linear pattern per unit area in a specified range irrespective of the type of a semiconductor integrated circuit device or by adjusting a process condition in accordance with type-to-type difference in the perimeter of the linear pattern per unit area.

Abstract: After an organic bottom anti-reflective coating (12) is deposited on an underlying film (11), a resist pattern (15) is formed on the organic bottom anti-reflective coating (12). Dry etching is performed with respect to the organic bottom anti-reflective coating (12) masked with the resist pattern (15) to form an anti-reflective coating pattern. The dry-etching of the organic bottom anti-reflective coating (12) is performed by using etching gas containing gas having the S component such as SO2/O2-based etching gas or COS/O2-based etching gas.

Abstract: Liquid water drops are formed around particles situated on a substrate and diffuse laser light patterns are intensified by the liquid water drops to make it possible to detect minute particles of 0.1 .mu.m and less in dimension.

Abstract: A method for fabricating a semiconductive device is described, wherein a semiconductive substrate having a thermally shrinkable, refractory metal silicide thin film is provided, on which an insulating film on the metal silicide thin film is formed. The metal silicide thin film is thermally treated in an atmosphere containing hydrogen. By this, no morphological degradation is observed in the silicide thin film without an increase of the resistance.

Abstract: Disclosed is a method for burying a step in a semiconductor substrate in which (1) SiO.sub.2 layer is formed on a lower part of the step, (2) photoresist layer with equal thickness to the height of the step on the SiO.sub.2 layer at a portion corresponding to the lower part of the step, (3) sputter-SiO.sub.2 layer is formed by sputtering on the photoresist layer and SiO.sub.2 layer, (4) another photoresist layer is formed on the sputter-SiO.sub.2 layer, (5) the another photoresist layer and sputter-SiO.sub.2 layer are removed, and (6) the SiO.sub.2 layer and photoresist layer are removed. By this method, semiconductor substrate with flatness of within 50 nm in a 6-inch wafer can be obtained.