Abstract: A comparator is presented. The comparator includes an input port for receiving an input voltage; an output port for providing an output voltage; a resistive divider, first and second transistors, and a differential amplifier. The resistive divider has a first node for providing a first voltage and a second node for providing a second voltage. The first transistor has a control terminal coupled to the first node, a first terminal coupled to the input port, and a second terminal coupled to a common node. The second transistor has a control terminal coupled to the second node, a first terminal coupled to the input port, and a second terminal coupled to the common node. The differential amplifier has a first input coupled to the first terminal of the first transistor, a second input coupled to the first terminal of the second transistor and an output coupled to the output port.

Abstract: A comparator is presented. The comparator includes an input port for receiving an input voltage; an output port for providing an output voltage; a resistive divider, first and second transistors, and a differential amplifier. The resistive divider has a first node for providing a first voltage and a second node for providing a second voltage. The first transistor has a control terminal coupled to the first node, a first terminal coupled to the input port, and a second terminal coupled to a common node. The second transistor has a control terminal coupled to the second node, a first terminal coupled to the input port, and a second terminal coupled to the common node. The differential amplifier has a first input coupled to the first terminal of the first transistor, a second input coupled to the first terminal of the second transistor and an output coupled to the output port.

Abstract: An inductor current emulation circuit for use with a switching converter in which regulating the output voltage includes comparing an output which varies with the difference between the output voltage and a reference voltage with a ‘ramp’ signal which emulates the current in the output inductor. A current sensing circuit produces an output which varies with the current in the switching element that is turned on during the ‘off’ time, an emulated current generator circuit produces the ‘ramp’ signal during both ‘off’ and ‘on’ times, a comparator circuit compares the ‘ramp’ signal with at least one threshold voltage which varies with the sensed current and toggles an output when the ‘ramp’ exceeds the thresholds, and a feedback circuit produces an output which adjusts the ‘ramp’ signal each time the comparator circuit output toggles until the ‘ramp’ signal no longer exceeds the threshold voltages.

Abstract: The present disclosure proposes a fully integrated accurate LED output current controlling circuit and method, which can be seamlessly combined with true PWM dimming. The current controlling circuit has an auto zero function in the light-emitting diode driver to eliminate offsets caused by the system, process variations, parasitic effects, dimming and so on in an LED driver application, and thus is capable of controlling the LED current with high accuracy. Moreover, the driver of the present disclosure does not require the use of external components such as an external resistor to regulate current accuracy.

Abstract: The present disclosure proposes a fully integrated accurate LED output current controlling circuit and method, which can be seamlessly combined with true PWM dimming. The current controlling circuit has an auto zero function in the light-emitting diode driver to eliminate offsets caused by the system, process variations, parasitic effects, dimming and so on in an LED driver application, and thus is capable of controlling the LED current with high accuracy. Moreover, the driver of the present disclosure does not require the use of external components such as an external resistor to regulate current accuracy.

Abstract: An ESD protection circuit for a switching power converter which includes a high-side switching element connected between a supply voltage and the switching node, and a low-side switching element connected between the switching node and a common node. A current conduction path couples an ESD event that occurs on the switching node to an ESD sense node, and an ESD sensing circuit coupled to the sense node generates a trigger signal when an ESD event is sensed. A first logic gate keeps the high-side switching element off when the trigger signal indicates the sensing of an ESD event, and a second logic gate causes the low-side switching element to turn on when an ESD event is sensed such that the low-side switching element provides a conductive discharge path between the switching node and common node.

Abstract: An H-bridge buck-boost converter includes a first half-bridge portion having at least one first transistor, an inductor portion connected to the first half-bridge portion at a first connection, a second half-bride portion connected to the inductor portion at a second connection, the second half-bridge portion having at least one second transistor, and a control portion configured to provide a first switching signal to a gate of the first transistor of the first half-bridge portion as a function of a voltage at the first connection.

Abstract: An ESD protection circuit for a switching power converter which includes a high-side switching element connected between a supply voltage and the switching node, and a low-side switching element connected between the switching node and a common node. A current conduction path couples an ESD event that occurs on the switching node to an ESD sense node, and an ESD sensing circuit coupled to the sense node generates a trigger signal when an ESD event is sensed. A first logic gate keeps the high-side switching element off when the trigger signal indicates the sensing of an ESD event, and a second logic gate causes the low-side switching element to turn on when an ESD event is sensed such that the low-side switching element provides a conductive discharge path between the switching node and common node.

Abstract: A circuit for improving transient response for a load coupled to a voltage regulator by employing both load current level information and the regulator's output voltage to control a loop that provides relatively faster and accurate regulation of the regulator's output voltage. The circuit includes an error amplifier that is coupled to a reference voltage and feedback resistors connected to the regulator's output voltage. This error amplifier outputs a compensation signal that is subsequently summed at a summing point with additional information regarding the amount of current flowing through the load. Then, this summed compensation signal is subsequently employed by a pulse width modulation (PWM) comparator and other components to regulate the regulator's output voltage with improved speed and accuracy. The circuit can be arranged in different topologies, including buck, boost, and buck/boost.

Abstract: An H-bridge buck-boost converter includes a first half-bridge portion having at least one first transistor, an inductor portion connected to the first half-bridge portion at a first connection, a second half-bride portion connected to the inductor portion at a second connection, the second half-bridge portion having at least one second transistor, and a control portion configured to provide a first switching signal to a gate of the first transistor of the first half-bridge portion as a function of a voltage at the first connection.

Abstract: A system and method are disclosed for maintaining an output voltage of a constant current source circuit. A constant current source circuit is provided that comprises a voltage regulator, a first feedback loop and a second feedback loop that are connected to the voltage regulator, and a sample and hold circuit that is connected to the second feedback loop. The voltage regulator regulates an output voltage VOUT to a reference voltage VREF using a first feedback voltage signal FB on the first feedback loop. The sample and hold circuit samples and holds a second feedback voltage signal VFB from the second feedback loop while the first feedback loop is connected. The voltage regulator regulates an output voltage VOUT to the second feedback reference voltage signal VFB when the first feedback loop is disconnected.

Abstract: A feed-forward path is combined with a feed-back path to produce an output signal representation of an input signal frequency. The feed-forward path adjusts the output signal representation in response to a change in the input signal frequency, and does so in a response time that is independent of the feed-back path. Input frequencies can be represented as voltages, and first and second input frequency ranges which differ from one another can both be represented in the same range of voltages.

Abstract: A current mode PWM buck regulator is provided. The regulator includes a top-side transistor, a bottom-side transistor, an inductor, a sample-and-hold circuit, a ramp generator, a PWM comparator, an error amplifier, and a current sense amplifier. A current through the low-side transistor is sensed by the current sense amplifier. Also, a current sense voltage provided by the current sense amplifier is sampled when the low-side transistor is on, and held when the low-side transistor is off. The ramp generator is arranged to generate a voltage ramp that emulates the upslope of the inductor current. Additionally, the sampled low-side transistor current is combined with the voltage ramp. The PWM comparator is arranged to provide a PWM signal by comparing the voltage ramp to a comparison signal provided by the error amplifier.

Abstract: A regulator is provided. The regulator includes a main switch, a synchronous switch, an inductor, a sample-and-hold circuit, a ramp generator, a PWM comparator, an error amplifier, and a current sense amplifier. A current through the synchronous switch is sensed by the current sense amplifier. Also, a current sense voltage provided by the current sense amplifier is sampled when the synchronous switch is on, and held when the synchronous switch is off. The ramp generator is arranged to generate a voltage ramp that emulates the slope of the inductor current while the synchronous switch is open. Additionally, the sampled synchronous switch current is combined with the voltage ramp. The PWM comparator is arranged to provide a PWM signal by comparing the voltage ramp to a comparison signal provided by the error amplifier.

Abstract: Method and circuit for automatic correction of emulated inductor current without knowledge of actual inductor current ramp for an emulated current mode (ECM) PWM switching regulator. In an ECM-PWM switching regulator a compensation ramp component is usually added to an up-slope. An excess ramp component may also be added compared to actual inductor current. According to one embodiment of the present invention, an integrating negative feedback circuit is employed to reduce both extra components. According to another embodiment, a single integrating negative feedback loop is added to the ECM-PWM regulator to retain the compensation ramp component while reducing the excess ramp component. According to a further embodiment, excess ramp component is reduced by adding the integrating negative feedback loop at an end stage of the circuit. Finally, the feedback loop with two duplicate track-and-hold circuitry may be added to reduce the excess ramp component, while retaining the compensation component.

Abstract: Method and circuit for automatic correction of emulated inductor current without knowledge of actual inductor current ramp for an emulated current mode (ECM) PWM switching regulator. In an ECM-PWM switching regulator a compensation ramp component is usually added to an up-slope. An excess ramp component may also be added compared to actual inductor current. According to one embodiment of the present invention, an integrating negative feedback circuit is employed to reduce both extra components. According to another embodiment, a single integrating negative feedback loop is added to the ECM-PWM regulator to retain the compensation ramp component while reducing the excess ramp component. According to a further embodiment, excess ramp component is reduced by adding the integrating negative feedback loop at an end stage of the circuit. Finally, the feedback loop with two duplicate track-and-hold circuitry may be added to reduce the excess ramp component, while retaining the compensation component.

Abstract: A current mode PWM buck regulator is provided. The regulator includes a top-side transistor, a bottom-side transistor, an inductor, a sample-and-hold circuit, a ramp generator, a PWM comparator, an error amplifier, and a current sense amplifier. A current through the low-side transistor is sensed by the current sense amplifier. Also, a current sense voltage provided by the current sense amplifier is sampled when the low-side transistor is on, and held when the low-side transistor is off. The ramp generator is arranged to generate a voltage ramp that emulates the upslope of the inductor current. Additionally, the sampled low-side transistor current is combined with the voltage ramp. The PWM comparator is arranged to provide a PWM signal by comparing the voltage ramp to a comparison signal provided by the error amplifier.

Abstract: A method and circuit for synchronizing an input clock signal with a plurality of internal clock signals in a multiple phase Pulse Width Modulation (PWM) switching power supply without using a Phase Locked Loop (PLL). A period of the input clock signal is measured by using a frequency to voltage converter. A reference capacitor charged by a constant current source is arranged to generate a reference voltage with a slope based on the period of the input clock signal. A change in the reference voltage across the reference capacitor is substantially inversely proportional to a frequency of the input clock. By providing the reference voltage to a sample-and-hold circuit and using an output of the sample-and-hold circuit to feed a comparator, synchronization may be accomplished. Each internal clock signal is generated by different reference capacitor and current source circuit.

Abstract: A current mode PWM buck regulator is provided. The regulator includes a top-side transistor, a bottom-side transistor, an inductor, a sample-and-hold circuit, a ramp generator, a PWM comparator, an error amplifier, and a current sense amplifier. A current through the low-side transistor is sensed by the current sense amplifier. Also, a current sense voltage provided by the current sense amplifier is sampled when the low-side transistor is on, and held when the low-side transistor is off. The ramp generator is arranged to generate a voltage ramp that emulates the upslope of the inductor current. Additionally, the sampled low-side transistor current is combined with the voltage ramp. The PWM comparator is arranged to provide a PWM signal by comparing the voltage ramp to a comparison signal provided by the error amplifier.