Patents by Inventor Kenji Ujiie
Kenji Ujiie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8316908Abstract: [Object] When press-bonding superposed curved glass plates together by a plurality of curved rolls, even if curvature of the curved glass changes, a preliminary bonding method and device of a laminated glass can cope with a variety of curvatures of the curved glass plate by an easy adjustment.Type: GrantFiled: June 16, 2009Date of Patent: November 27, 2012Assignee: Central Glass Company, LimitedInventors: Kenji Ujiie, Yoshiki Katada, Koji Tamai, Chikao Nakashima
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Publication number: 20120073417Abstract: [Task] A sheet material is cut in a predetermined closed loop shape. [Means for solving task] A cutting apparatus for a sheet material, comprises: an air table which is capable of ejecting or sucking air through a plurality of minute punching sections thereof; a template having at least one recess groove section in a predetermined closed loop shape mounted and fixed onto the air table and a punching section located at each of positions on the template which is coincident with a position of each of the punching sections of the air table; a cutter blade disposed on an upper position of the sheet material mounted on the template to cut the sheet material along the recess groove section of the template; and cutter blade driving means which is capable of moving and rotating the cutter blade in X, Y, and Z coordinate axes.Type: ApplicationFiled: June 2, 2010Publication date: March 29, 2012Applicant: Central Glass Company, LimitedInventors: Kenji Ujiie, Koji Tamai, Chikao Nakashima
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Publication number: 20110100530Abstract: [Object] When press-bonding superposed curved glass plates together by a plurality of curved rolls, even if curvature of the curved glass changes, a preliminary bonding method and device of a laminated glass can cope with a variety of curvatures of the curved glass plate by an easy adjustment.Type: ApplicationFiled: June 16, 2009Publication date: May 5, 2011Inventors: Kenji Ujiie, Yoshiki Katada, Koji Tamai, Chikao Nakashima
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Patent number: 7497096Abstract: An apparatus for conveying a curved glass sheet includes a disk roll conveyor and a roll conveyor set positioned downstream of the disk roll conveyor. The roll conveyor set has a plurality of roll conveyor units. In this apparatus, first and second adjusting devices are operable to provide the curved glass sheet with (a) a first conveyance route in which the disk roll conveyor and the roll conveyor set are in a horizontal position to provide a smooth horizontal conveyance surface or (b) a second conveyance route in which the disk roll conveyor is in a downward position and in which at least one roll conveyor unit at a downstream side of the roll conveyor set is in an upward position to provide a continuous concave conveyance surface.Type: GrantFiled: March 4, 2004Date of Patent: March 3, 2009Assignee: Central Glass Company, LimitedInventors: Osamu Asai, Yoshiki Katada, Kenji Ujiie
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Patent number: 7371606Abstract: The yield of a sealing process for a semiconductor device which adopts a flip-chip mounting method is to be improved. In a molding process wherein plural semiconductor chip ICs mounted on a parts mounting surface of a substrate matrix through bump electrodes are to be sealed all together with a sealing resin in a reduced state of the internal pressure of a cavity of a molding apparatus, a clamping pressure at the time of clamping the substrate matrix by both a lower die and an upper die of a molding die is set at a relatively low pressure in an initial stage of injection of the sealing resin and is changed to a relatively high pressure when the sealing resin has covered the semiconductor chip ICs located in a final stage in the resin injecting direction.Type: GrantFiled: December 16, 2004Date of Patent: May 13, 2008Assignee: Renesas Technology Corp.Inventors: Kenji Ujiie, Bunji Kuratomi
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Patent number: 7057283Abstract: A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device. The electrically insulating layer is formed with a thickness so as to provide ?-ray shielding of the semiconductor device.Type: GrantFiled: April 16, 2004Date of Patent: June 6, 2006Assignee: Hitachi, Ltd.Inventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
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Patent number: 6930388Abstract: A semiconductor device is provided which enables a flip chip connection without use of underfill. The semiconductor device includes a semiconductor element having circuit electrodes and a circuit surface coated with a protecting film. A stress relaxation layer is provided by coating a cured thermoplastic resin onto the protecting film of the circuit surface in a manner which leaves the circuit electrodes exposed and curing it and having an inclination in the edge portion thereof. A wiring layer with wirings is connected to each of the circuit electrodes and disposed so as to make an electrical connection from the circuit electrodes, via the edge portion of the stress relaxation layer, and to a desired portion on the surface of the stress relaxation layer. A protecting film is provided thereon, and an external connection terminal is also provided.Type: GrantFiled: March 20, 2001Date of Patent: August 16, 2005Assignee: Renesas Technology Corp.Inventors: Yoshihide Yamaguchi, Hiroyuki Tenmei, Kosuke Inoue, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Naoya Kanda, Madoka Minagawa, Ichiro Anjo, Asao Nishimura, Kenji Ujiie, Akira Yajima
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Publication number: 20050133895Abstract: The yield of a sealing process for a semiconductor device which adopts a flip-chip mounting method is to be improved. In a molding process wherein plural semiconductor chip ICs mounted on a parts mounting surface of a substrate matrix through bump electrodes are to be sealed all together with a sealing resin in a reduced state of the internal pressure of a cavity of a molding apparatus, a clamping pressure at the time of clamping the substrate matrix by both a lower die and an upper die of a molding die is set at a relatively low pressure in an initial stage of injection of the sealing resin and is changed to a relatively high pressure when the sealing resin has covered the semiconductor chip ICs located in a final stage in the resin injecting direction.Type: ApplicationFiled: December 16, 2004Publication date: June 23, 2005Inventors: Kenji Ujiie, Bunji Kuratomi
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Patent number: 6867502Abstract: A flip-chip BGA is disclosed which exhibits an excellent high-speed electric transmission characteristic while minimizing the formation of voids in sealing resin filled between a semiconductor chip and a wiring substrate. A silicon chip is flip-chip-mounted on a package substrate, and in a central area of a main surface of the silicon chip are arranged a power supply circuit, an input/output circuit, and plural bonding pads, while in the other area than the central area are arranged solder bumps in a matrix form, the solder bumps being electrically connected to the bonding pads through Cu wiring. Of the solder bumps, solder bumps for input/output power supply and solder bumps for the input and output of a data signal are arranged in a first area adjacent to the central area, and solder bumps for address signal input are arranged in a second area located outside the first area.Type: GrantFiled: February 21, 2003Date of Patent: March 15, 2005Assignee: Renesas Technology Corp.Inventors: Mitsuaki Katagiri, Masami Usami, Kenji Ujiie
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Publication number: 20040261456Abstract: An apparatus for conveying a curved glass sheet includes a disk roll conveyor and a roll conveyor set positioned downstream of the disk roll conveyor. The roll conveyor set has a plurality of roll conveyor units. In this apparatus, first and second adjusting devices are operable to provide the curved glass sheet with (a) a first conveyance route in which the disk roll conveyor and the roll conveyor set are in a horizontal position to provide a smooth horizontal conveyance surface or (b) a second conveyance route in which the disk roll conveyor is in a downward position and in which at least one roll conveyor unit at a downstream side of the roll conveyor set is in an upward position to provide a continuous concave conveyance surface.Type: ApplicationFiled: March 4, 2004Publication date: December 30, 2004Applicant: Central Glass Company, LimitedInventors: Osamu Asai, Yoshiki Katada, Kenji Ujiie
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Patent number: 6822317Abstract: A semiconductor apparatus comprising a semiconductor device, an electrically insulating layer formed on the semiconductor device, and an external connection terminal formed on the electrically insulating layer and electrically connected to an electrode of the semiconductor device, wherein a power/ground line and a signal line in a region of from an edge of the electrically insulating layer to a uniform-thickness flat portion of the electrically insulating layer are different in kind of wiring pattern from each other.Type: GrantFiled: October 30, 2000Date of Patent: November 23, 2004Assignee: Renesas Technology CorporationInventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
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Publication number: 20040195687Abstract: A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device. The electrically insulating layer is formed with a thickness so as to provide &agr;-ray shielding of the semiconductor device.Type: ApplicationFiled: April 16, 2004Publication date: October 7, 2004Inventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
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Patent number: 6770547Abstract: A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device.Type: GrantFiled: October 30, 2000Date of Patent: August 3, 2004Assignee: Renesas Technology CorporationInventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
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Patent number: 6661093Abstract: For preventing &agr;-rays induced soft errors in a semiconductor device in which solder bumps are connected with Cu wirings formed on Al wirings, bump lands connected with solder bumps and Cu wirings connected integrally therewith are constituted of a stacked film of a Cu film and an Ni film formed thereon, the thickness of the stacked film is larger than the thickness of the photosensitive polyimide resin film, the thickness of the inorganic passivation film, the thickness of the third Al wiring layer and the bonding pad and the thickness of the second interlayer insulative film formed below the Cu wirings and the bump land, that is, the bump land being constituted with such a thickness as larger than any of the thickness for the insulation material and the wiring material interposed between the MISFET (n-channel MISFET and p-channel MISFET) constituting the memory cell and the bump land.Type: GrantFiled: November 20, 2001Date of Patent: December 9, 2003Assignee: Renesas Technology CorporationInventors: Kenji Ujiie, Kenichi Yamamoto, Junichi Arita
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Patent number: 6624504Abstract: A semiconductor apparatus includes a semiconductor device having circuit electrodes aligned centrally of the semiconductor apparatus. A first electrically insulating layer is formed on said semiconductor device with said circuit electrodes being exposed from said first insulating layer. A second electrically insulating layer is formed on said first insulating layer, and external connection terminals are formed on said second insulating layer. A wiring is formed on said second insulating layer to electrically connect said external connect terminals to said circuit electrodes of said semiconductor device, and a third electrically insulating layer is formed on said second insulating layer and on said wiring. Particles are provided in the second insulating layer to control a shape of said second insulating layer.Type: GrantFiled: October 30, 2000Date of Patent: September 23, 2003Assignee: Hitachi, Ltd.Inventors: Kosuke Inoue, Hiroyuki Tenmei, Yoshihide Yamaguchi, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Madoka Minagawa, Naoya Kanda, Ichiro Anjo, Asao Nishimura, Akira Yajima, Kenji Ujiie
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Publication number: 20030168748Abstract: A flip-chip BGA is disclosed which exhibits an excellent high-speed electric transmission characteristic while minimizing the formation of voids in sealing resin filled between a semiconductor chip and a wiring substrate. A silicon chip is flip-chip-mounted on a package substrate, and in a central area of a main surface of the silicon chip are arranged a power supply circuit, an input/output circuit, and plural bonding pads, while in the other area than the central area are arranged solder bumps in a matrix form, the solder bumps being electrically connected to the bonding pads through Cu wiring. Of the solder bumps, solder bumps for input/output power supply and solder bumps for the input and output of a data signal are arranged in a first area adjacent to the central area, and solder bumps for address signal input are arranged in a second area located outside the first area.Type: ApplicationFiled: February 21, 2003Publication date: September 11, 2003Inventors: Mitsuaki Katagiri, Masami Usami, Kenji Ujiie
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Publication number: 20020074656Abstract: For preventing &agr;-rays induced soft errors in a semiconductor device in which solder bumps are connected with Cu wirings formed on Al wirings, bump lands connected with solder bumps and Cu wirings connected integrally therewith are constituted of a stacked film of a Cu film and an Ni film formed thereon, the thickness of the stacked film is larger than the thickness of the photosensitive polyimide resin film, the thickness of the inorganic passivation film, the thickness of the third Al wiring layer and the bonding pad and the thickness of the second interlayer insulative film formed below the Cu wirings and the bump land, that is, the bump land being constituted with such a thickness as larger than any of the thickness for the insulation material and the wiring material interposed between the MISFET (n-channel MISFET and p-channel MISFET) constituting the memory cell and the bump land.Type: ApplicationFiled: November 20, 2001Publication date: June 20, 2002Applicant: Hitachi, Ltd.Inventors: Kenji Ujiie, Kenichi Yamamoto, Junichi Arita
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Publication number: 20020063332Abstract: The object of the present invention is to realize a semiconductor device enabling a flip chip connection without use of underfill.Type: ApplicationFiled: March 20, 2001Publication date: May 30, 2002Inventors: Yoshihide Yamaguchi, Hiroyuki Tenmei, Kosuke Inoue, Noriyuki Oroku, Hiroshi Hozoji, Shigeharu Tsunoda, Naoya Kanda, Madoka Minagawa, Ichiro Anjo, Asao Nishimura, Kenji Ujiie, Akira Yajima
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Patent number: 4973348Abstract: This invention relates to a mold carriage for carrying thereon a mold for bending a glass sheet, or a stack of glass sheets to be laminated, placed thereon into a curved shape by heating in a furnace. To locally intensely heat the glass sheet in a selected area to be bent sharply relative to the major area, the mold carriage is installed with a heater to heat a selected area of the glass sheet from underneath, a holder to hold the heater and adjust the position of the heater, and a heater support to support thereon an external heater which is suspended from a separate member disposed in the furnace to heat the afore-mentioned area of the glass sheet from above. The heater support also can adjust the position of the external heater.Type: GrantFiled: October 19, 1989Date of Patent: November 27, 1990Assignee: Central Glass Company, LimitedInventors: Kenji Ujiie, Masami Nishitani
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Patent number: 4664692Abstract: A gas hearth furnace for heat treatment of a plate glass consists of a plurality of aligned hearth beds on which a plate glass moves to be subjected to heat treatment. Four support pillars are provided for supporting each hearth bed through a pair of support blocks disposed along the opposite sides of the lower surface of the hearth bed. Each support pillar and each support block are made of a refractory having a coefficient of thermal expansion not higher than 10.sup.-7 /.degree. C., thereby rendering negligible the fluctuation of vertical location of the hearth beds due to thermal expansion of a support structure including the support pillar and block.Type: GrantFiled: April 11, 1986Date of Patent: May 12, 1987Assignee: Central Glass Company, LimitedInventors: Katsuyasu Simomura, Kenji Ujiie