Patents by Inventor Kenji Yokoyama
Kenji Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 4238737Abstract: A biasing arrangement comprising: a pair of gate biasing resistors for Field Effect Transistors forming a push-pull amplifier, and a constant-current supplying means having two output terminals for supplying stabilized gate bias voltages to the transistors. The constant-current supplying means can be adjusted manually or automatically for setting a suitable operation point of the transistors and for balancing their bias voltages. By this arrangement, amplifiers can have a simplified structure. This arrangement greatly simplifies biasing means which also can be easily regulated.Type: GrantFiled: July 31, 1978Date of Patent: December 9, 1980Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 4223273Abstract: A power amplifier device comprising first and second output terminals connected to a loudspeaker, and a power amplifier having a non-inverting input supplied with an audio signal, an output connected to the first output terminal and an inverting input. The second output terminal is grounded through a first resistor and connected to an input of an inverting amplifier having a gain of -1. An output of the inverting amplifier is connected to the inverting input of the power amplifier through a second resistor. The output of the power amplifier is connected to its inverting input through a third resistor. The ratio of the third resistor to the second resistor is selected to be larger than 1 whereby the output impedance of the power amplifier device as seen from the first and second output terminals is made to be negative.Type: GrantFiled: November 3, 1978Date of Patent: September 16, 1980Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 4222012Abstract: In an amplifier device having a resistor inserted between an input terminal and the ground, a signal whose phase is opposite to that of an input signal is applied to the resistor, whereby the effect of thermal noise which may be generated by the resistor is minimized to improve the S/N ratio.Type: GrantFiled: June 15, 1978Date of Patent: September 9, 1980Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 4206419Abstract: A power amplifier comprises: a complementary symmetry push-pull circuit formed with two complementary transistors mutually coupled at their emitters and having an operating point for Class-A mode operation; a floating power supply having a neutral terminal serving as the output terminal of the power amplifier, a positive and a negative terminal connected respectively to the collectors of the respective transistors; a bootstrapping circuit for driving the mutually coupled emitters in proportion to the potential at the output terminal; and a circuit for negative feedback of signal from the output terminal to the bases of the transistors.Type: GrantFiled: January 8, 1979Date of Patent: June 3, 1980Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 4151477Abstract: A tone control circuit for stereophonic amplifiers, guitar amplifiers and the like is disclosed. The tone control circuit includes a bass circuit having a first variable resistor whose movable contact is connected to an output terminal of an amplifier circuit, two resistors equal in resistance connected respectively to two end terminals of the variable resistor, and a capacitor shunting the variable resistor. The tone control circuit also includes a treble circuit having a second variable resistor, a resistor, and a capacitor. The treble circuit is connected in parallel to the bass circuit in such a manner that the gain in a particular frequency range of the amplifier circuit can be changed by varying the resistances of the two variable resistors.Type: GrantFiled: September 23, 1977Date of Patent: April 24, 1979Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 4137506Abstract: A compound transistor all of the first conductivity type circuitry having a high input impedance as well as a high gain, comprises a first, a second and a third bipolar transistor, and a fourth bipolar transistor complementary to at least the first transistor, the second and third transistors having their emitters coupled together to a first terminal and having their bases connected together and further connected to the collector of the fourth transistor, the bases of the first and fourth transistors being connected in common to a second terminal, the emitter of the first transistor being connected to the collector of the second transistor, the collector of the first transistor and the emitter of the fourth transistor being connected together to a third terminal.Type: GrantFiled: October 27, 1977Date of Patent: January 30, 1979Assignee: Nippon Gakki Seizo Kabushiki KaishaInventors: Masayuki Iwamatsu, Kenji Yokoyama
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Patent number: 4115742Abstract: An emitter follower type power amplifier capable of changing over supply voltage and hence the load line, comprising: an amplifying transistor of saturating type; at least a first and a second supply voltage source; a switching transistor having, a collector connected to the first supply voltage source, and an emitter connected to the second supply voltage source via a diode and also to the collector of said power amplifying transistor; a load resistor connected between the emitter of the power amplifying transistor and the ground; and a biasing voltage source connected between the base of the switching transistor and the emitter of the power amplifying transistor. This power amplifier circuit arrangement allows switching-over between load lines for small signal region and large signal region thereby enabling large signal amplification and reducing the collector loss of the power amplifying transistor. This circuit arrangement is also used in a push-pull power amplifying circuit to obtain the same advantage.Type: GrantFiled: March 18, 1977Date of Patent: September 19, 1978Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 4103245Abstract: A transistor amplifier circuitry for low level signal which employs, as the amplifying element of at least its input state circuit, a transistor having a low input resistance. Thus, this transistor amplifier circuitry has a true (not apparent) input resistance sufficiently lower than the impedance of a signal source which may be connected to the transistor amplifier circuitry. Therefore, this transistor amplifier circuitry for low level signal is capable of amplifying, with a high S/N ratio, the signal from the signal source of a low impedance.Type: GrantFiled: August 17, 1976Date of Patent: July 25, 1978Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 4100438Abstract: A compound transistor circuitry having an output characteristic resembling that of a pentode vacuum tube comprises: a first field effect transistor having a saturated-type output characteristic resembling that of a pentode vacuum tube; and a second field effect transistor having an unsaturated-type output characteristic resembling that of a triode vacuum tube. The first and second field effect transistors have a conducting channel of a single and same conductivity type, respectively. The second field effect transistor is connected in series with the drain current path of the first field effect transistor. This second field effect transistor is rendered conductive only when the drain-source voltage of the first field effect transistor exceeds its pinch-off voltage.Type: GrantFiled: August 14, 1975Date of Patent: July 11, 1978Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 4093925Abstract: A method and a system of obtaining a large power with the use of a junction field effect transistor by extending the working range to improve the utilization rate of the power source voltage. The range for the gate voltage is set up to some predetermined forward voltage at which the gate and the source will be subjected to a forward biasing. The source-to-drain internal resistance is reduced by this forward gate voltage, but no gate current is allowed to flow probably due to the existence of a non-linear element between the gate and the source.Type: GrantFiled: November 18, 1975Date of Patent: June 6, 1978Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 4087760Abstract: A transistor amplifier circuit comprising a pair of complementary transistors having collectors connected to each other through a resistor and to an output terminal through respective capacitors, emitters connected to a positive and a negative supply voltage respectively and bases connected to the collectors thereof through respective resistors and to an input terminal through respective capacitors. In this amplifier circuit, the emitter circuits of the paired-transistors include no resistors and accordingly no by-pass capacitors, thus eliminating thermal noise sources and also voltage drop due to such resistors. Therefore, this amplifier circuit can be operated at a markedly reduced S/N ratio with a very low supply voltage, giving a high utility of voltage. Such amplifier circuit can have a very simplified structure.Type: GrantFiled: February 8, 1977Date of Patent: May 2, 1978Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 4057764Abstract: An amplifier comprises a power amplifying circuit including FET's and operable when supplied with a first power source and a drive circuit operable when supplied with a second power source for driving the power amplifying circuit and including a bias circuit for providing bias voltages for the FET's. Upon turning on the power switch, the first power source builds up quickly while the second power source builds up with some time delay. Switch-over circuits connect the power lines of the drive circuit to the first power source initially and to the second power source after the build-up of the latter, thereby starting the supply of the bias voltages to the FET's at the build up of the first power source to prevent an excessively large current or rush current from flowing through the FET's, thus avoiding the breakage or characteristic deterioration of the FET's.Type: GrantFiled: March 16, 1976Date of Patent: November 8, 1977Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 4037166Abstract: A biasing arrangement comprising: a first transistor for driving a pair of field effect transistors (FET's) jointly forming a push-pull amplifier; a second transistor connected in series in the collector circuit of the first transistor, the voltage across the second transistor being applied as the gate-bias voltage for the FET's; and a constant current source connected to the base of the second transistor for causing a substantially constant current to flow through a resistor connected between the collector and base of the second transistor. With this arrangement, across the resistor is developed a stabilized sufficiently large voltage as compared with the base to emitter voltage of the second transistor. Thus, the gate bias voltages of the FET's are stabilized against the fluctuations of the ambient temperature.Type: GrantFiled: March 16, 1976Date of Patent: July 19, 1977Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 4035669Abstract: A switching circuit designed to start operation after the lapse of a predetermined delay time from its connection to a power source. The switching circuit has a switch element which is rendered conductive when the terminal voltage of a capacitor of a time constant circuit connected to the power source for determining the delay time has reached a predetermined value. Thereafter the electric charge of said capacitor is quickly discharged through a low impedance discharge line including said switch element.Type: GrantFiled: November 18, 1975Date of Patent: July 12, 1977Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 4017434Abstract: A diallyl phthalate resin-containing aqueous emulsion containing an aqueous emulsion of a diallyl phthalate resin of a rate of polymerization of 30 - 75 weight % consisting of 50 - 100 weight % of diallyl phthalate and 50 - 0 weight % of an alkyl acrylate, and an aqueous emulsion of a thermosetting vinyl resin consisting of 10 - 1 weight % of a vinyl compound containing a thermosetting functional group and 90 - 99 weight % of a vinyl compound not containing a thermosetting functional group, the content of said diallyl phthalate resin component to said thermosetting vinyl resin component being in a proportion of 10 - 70 weight % of the former to 90 - 30 weight % of the latter.Type: GrantFiled: December 1, 1975Date of Patent: April 12, 1977Assignee: Osaka Soda Co., Ltd.Inventors: Akio Suzui, Shinji Nose, Takashi Kodama, Kenji Yokoyama, Kazuya Matsumoto, Yoshiharu Fujio
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Patent number: 4015214Abstract: A push-pull transistor amplifier having a preamplification stage consisting of complementary symmetry transistors. The quiescent operating points of the transistors are stabilized by the provision of a constant-current circuitry connected between the source electrodes of both transistors.Type: GrantFiled: April 3, 1975Date of Patent: March 29, 1977Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 4005353Abstract: In series in a load current path between an input terminal and an output terminal is connected a variable resistance element having a control terminal to constitute a series-type direct current voltage regulating circuitry. An error amplifier includes a field effect transistor (FET) having a triode characteristic, a constant current circuit as a load in the drain circuit and a variable resistor in the source circuit to provide a variable reference voltage. The voltage at the output terminal is divided by a resistor network and applied to the gate of FET. The drain voltage of the FET is applied to the control terminal of the variable resistance element. Such a configuration provides a simple circuit arrangement and an excellent voltage regulation.Type: GrantFiled: April 23, 1975Date of Patent: January 25, 1977Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 3987369Abstract: A direct-coupled full stage cascaded amplifier comprising an output stage, a drive stage and a predrive stage. The output stage is composed of an SEPP (single-ended push-pull) circuit of a plurality of FET's having a certain conductivity type channel. The drive stage is composed of a differential amplifier circuit of a plurality of FET's having a channel of a conductivity type same as that of the FET's in the output stage. The pre-drive stage is composed of another differential amplifier circuit of a plurality of FET's having a channel of a conductivity type opposite to that of the FET's in the output stage. The source electrodes of the FET's in the respective differential amplifier circuits are connected via constant current circuits, respectively, to voltage supply lines having opposite polarities.Type: GrantFiled: May 20, 1975Date of Patent: October 19, 1976Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 3986134Abstract: A push-pull amplifier circuitry comprising: a first and a second FET (abbreviation of field effect transistor which will be used hereinafter) of an n-channel type, a third FET of a p-channel type with its gate and source connected to the gate of said first FET and to the source of said second FET respectively, a fourth FET of a p-channel type having a gate and a source connected to the gate of said second FET and to the source of said first FET, a positive voltage supply connected to the drain of said first FET and via a resistor to the drain of said second FET and, a negative voltage supply connected to the drain of said third FET and via another resistor to the drain of said fourth FET. This circuitry is suitable for use as an input stage or an interstage amplifier circuit such as a pre-driver of a multistage direct-coupled push-pull amplifier.Type: GrantFiled: August 15, 1975Date of Patent: October 12, 1976Assignee: Nippon Gakki Seizo Kabushiki KaishaInventor: Kenji Yokoyama
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Patent number: 3963661Abstract: A diallyl phthalate resin-containing aqueous emulsion containing an aqueous emulsion of a diallyl phthalate resin of a rate of polymerization of 30 - 75 weight % consisting of 50 - 100 weight % of diallyl phthalate and 50 - 0 weight % of an alkyl acrylate, and an aqueous emulsion of a thermosetting vinyl resin consisting of 10 - 1 weight % of a vinyl compound containing a thermosetting functional group and 90 - 99 weight % of a vinyl compound not containing a thermosetting functional group, the content of said diallyl phthalate resin component to said thermosetting vinyl resin component being in a proportion of 10 - 70 weight % of the former to 90 - 30 weight % of the latter.Type: GrantFiled: July 16, 1974Date of Patent: June 15, 1976Assignee: Osaka Soda Co., Ltd.Inventors: Akio Suzui, Shinji Nose, Takashi Kodama, Kenji Yokoyama, Kazuya Matsumoto, Yoshiharu Fujio