Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.

Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.

Abstract: A semiconductor device including a FIFO circuit in which a data capacity can be increased while minimizing an increase in a circuit scale is provided. The semiconductor device includes a single-port type storage unit (11) which stores data, a flip-flop (12) which temporarily stores write data (FIFO input) or read data (FIFO output) of the storage unit (11), and a control unit (14, 40) which controls a write timing of a data signal, which is stored in the flip-flop (12), to the storage unit (11) or a read timing of the data signal from the storage unit to avoid an overlap between a write operation and a read operation in the storage unit (11).

Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.

Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.

Abstract: A semiconductor device including a FIFO circuit in which a data capacity can be increased while minimizing an increase in a circuit scale is provided. The semiconductor device includes a single-port type storage unit (11) which stores data, a flip-flop (12) which temporarily stores write data (FIFO input) or read data (FIFO output) of the storage unit (11), and a control unit (14, 40) which controls a write timing of a data signal, which is stored in the flip-flop (12), to the storage unit (11) or a read timing of the data signal from the storage unit to avoid an overlap between a write operation and a read operation in the storage unit (11).

Abstract: A semiconductor device including a FIFO circuit in which a data capacity can be increased while minimizing an increase in a circuit scale is provided. The semiconductor device includes a single-port type storage unit (11) which stores data, a flip-flop (12) which temporarily stores write data (FIFO input) or read data (FIFO output) of the storage unit (11), and a control unit (14, 40) which controls a write timing of a data signal, which is stored in the flip-flop (12), to the storage unit (11) or a read timing of the data signal from the storage unit to avoid an overlap between a write operation and a read operation in the storage unit (11).

Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.

Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.

Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.

Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.

Abstract: A semiconductor device including a FIFO circuit in which a data capacity can be increased while minimizing an increase in a circuit scale is provided. The semiconductor device includes a single-port type storage unit (11) which stores data, a flip-flop (12) which temporarily stores write data (FIFO input) or read data (FIFO output) of the storage unit (11), and a control unit (14, 40) which controls a write timing of a data signal, which is stored in the flip-flop (12), to the storage unit (11) or a read timing of the data signal from the storage unit to avoid an overlap between a write operation and a read operation in the storage unit (11).

Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.

Abstract: A PWM (Pulse Width Modulation) signal outputting circuit includes a counting unit for counting a number of clocks to output a counter value, and for resetting the counter value to resume counting when a reset signal is input to the counting unit; a dead time value storage unit for storing a dead time value; and a plurality of PWM signal outputting units for setting a start setting value and a termination setting value. The PWM signal outputting unit generates a termination signal and a start signal. Further, the PWM signal outputting unit is configured to output a PWM signal, which is raised according to the start signal generated by itself and is decreased according to the termination signal generated by itself. Further, the PWM signal outputting units is configured to generate the termination signal when the counter value matches to the termination setting value generated by itself.

Abstract: A PWM (Pulse Width Modulation) signal outputting circuit includes a counting unit for counting a number of clocks to output a counter value, and for resetting the counter value to resume counting when a reset signal is input to the counting unit; a dead time value storage unit for storing a dead time value; and a plurality of PWM signal outputting units for setting a start setting value and a termination setting value. The PWM signal outputting unit generates a termination signal and a start signal. Further, the PWM signal outputting unit is configured to output a PWM signal, which is raised according to the start signal generated by itself and is decreased according to the termination signal generated by itself. Further, the PWM signal outputting units is configured to generate the termination signal when the counter value matches to the termination setting value generated by itself.

Abstract: A digital filter circuit is capable of processing multi-channel data having different sampling frequencies. RAMs (random access memories) are provided which store data inputted thereto respectively, and the data outputted from the RAMs are alternately processed.

Abstract: A digital filter includes a data storage section, a filter coefficient storage section, a multiplier, an accumulative adder section, a data output section and a control section. The data storage section stores the latest multiple input data for every channel and outputs the stored input data in response to a selection signal. The filter coefficient storage section stores predetermined filter coefficient corresponding to the multiple input data. The accumulative adder section adds the result of multiplication of multiple data from the multiplier for every channel. The data output section holds the result of addition in the accumulative adder section and outputting output data.

Abstract: A circuit for testing an analog-digital converter includes: a subtracter which receives a converted value having a plurality of bits outputted from the analog-digital converter and an expected value having a plurality of bits, the subtracter calculating a difference value having a plurality of bits between the converted value and the expected value; and a logical operation circuit which receives the difference value, the logical operation circuit performing an exclusive-NOR operation between adjacent bits in the plurality of bits constituting the difference value, thereby outputting an exclusive-NOR value having a plurality of bits.

Abstract: A reproducing apparatus according to the present invention includes a thinning-out unit for thinning out part of a plurality of continuous audio digital data, and a conversion unit for simply increasing or decreasing variations in the amplitude of either continuous plural data including the data immediately preceding the thinned data or continuous plural data including the data immediately following the thinned data so that the data immediately preceding the thinned data will be concatenated with the data immediately following the thinned data along a smooth amplitude-varying curve.

Abstract: A signal generating circuit that enables to set an initial oscillation signal level to zero is provided. The circuit includes an adder 11, a first multiplier 12 with an multiplication coefficient of A1, a second multiplier 13 with an multiplication coefficient of A2, a first and second delay element 14, 15 and an initializing circuit 16. Output signal from an output terminal of the circuit is supplied to the first delay element 14, the output of it is supplied to the second delay element and the first multiplier 12. The output signal of the second delay element 15 is supplied to the second multiplier 13, the output signal of the first and second multiplier are supplied to the adder 11. The output of it is supplied to the output terminal. The initializing circuit outputs an initial value y1 and y2 of the first and second delay element such that it satisfies an equation y1*A1+y2*A2=0.