Patents by Inventor Kenjiro Matoba

Kenjiro Matoba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240152173
    Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 9, 2024
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Kenjiro MATOBA, Kazuhiro YAMASHITA
  • Patent number: 11907003
    Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: February 20, 2024
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Kenjiro Matoba, Kazuhiro Yamashita
  • Publication number: 20230152839
    Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 18, 2023
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Kenjiro MATOBA, Kazuhiro YAMASHITA
  • Patent number: 11567526
    Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: January 31, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Kenjiro Matoba, Kazuhiro Yamashita
  • Patent number: 11562775
    Abstract: A semiconductor device including a FIFO circuit in which a data capacity can be increased while minimizing an increase in a circuit scale is provided. The semiconductor device includes a single-port type storage unit (11) which stores data, a flip-flop (12) which temporarily stores write data (FIFO input) or read data (FIFO output) of the storage unit (11), and a control unit (14, 40) which controls a write timing of a data signal, which is stored in the flip-flop (12), to the storage unit (11) or a read timing of the data signal from the storage unit to avoid an overlap between a write operation and a read operation in the storage unit (11).
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 24, 2023
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Kenjiro Matoba
  • Publication number: 20220261031
    Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
    Type: Application
    Filed: May 5, 2022
    Publication date: August 18, 2022
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Kenjiro MATOBA, Kazuhiro YAMASHITA
  • Patent number: 11347257
    Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: May 31, 2022
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Kenjiro Matoba, Kazuhiro Yamashita
  • Publication number: 20210398570
    Abstract: A semiconductor device including a FIFO circuit in which a data capacity can be increased while minimizing an increase in a circuit scale is provided. The semiconductor device includes a single-port type storage unit (11) which stores data, a flip-flop (12) which temporarily stores write data (FIFO input) or read data (FIFO output) of the storage unit (11), and a control unit (14, 40) which controls a write timing of a data signal, which is stored in the flip-flop (12), to the storage unit (11) or a read timing of the data signal from the storage unit to avoid an overlap between a write operation and a read operation in the storage unit (11).
    Type: Application
    Filed: August 31, 2021
    Publication date: December 23, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: KENJIRO MATOBA
  • Patent number: 11127439
    Abstract: A semiconductor device including a FIFO circuit in which a data capacity can be increased while minimizing an increase in a circuit scale is provided. The semiconductor device includes a single-port type storage unit (11) which stores data, a flip-flop (12) which temporarily stores write data (FIFO input) or read data (FIFO output) of the storage unit (11), and a control unit (14, 40) which controls a write timing of a data signal, which is stored in the flip-flop (12), to the storage unit (11) or a read timing of the data signal from the storage unit to avoid an overlap between a write operation and a read operation in the storage unit (11).
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: September 21, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Kenjiro Matoba
  • Publication number: 20210240216
    Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
    Type: Application
    Filed: April 21, 2021
    Publication date: August 5, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Kenjiro MATOBA, Kazuhiro YAMASHITA
  • Patent number: 11068016
    Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: July 20, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Kenjiro Matoba, Kazuhiro Yamashita
  • Patent number: 11009904
    Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: May 18, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Kenjiro Matoba, Kazuhiro Yamashita
  • Publication number: 20200356132
    Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
    Type: Application
    Filed: July 29, 2020
    Publication date: November 12, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Kenjiro MATOBA, Kazuhiro YAMASHITA
  • Publication number: 20200312383
    Abstract: A semiconductor device including a FIFO circuit in which a data capacity can be increased while minimizing an increase in a circuit scale is provided. The semiconductor device includes a single-port type storage unit (11) which stores data, a flip-flop (12) which temporarily stores write data (FIFO input) or read data (FIFO output) of the storage unit (11), and a control unit (14, 40) which controls a write timing of a data signal, which is stored in the flip-flop (12), to the storage unit (11) or a read timing of the data signal from the storage unit to avoid an overlap between a write operation and a read operation in the storage unit (11).
    Type: Application
    Filed: March 18, 2020
    Publication date: October 1, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: KENJIRO MATOBA
  • Publication number: 20180054202
    Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.
    Type: Application
    Filed: August 16, 2017
    Publication date: February 22, 2018
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Kenjiro MATOBA, Kazuhiro YAMASHITA
  • Patent number: 9184738
    Abstract: A PWM (Pulse Width Modulation) signal outputting circuit includes a counting unit for counting a number of clocks to output a counter value, and for resetting the counter value to resume counting when a reset signal is input to the counting unit; a dead time value storage unit for storing a dead time value; and a plurality of PWM signal outputting units for setting a start setting value and a termination setting value. The PWM signal outputting unit generates a termination signal and a start signal. Further, the PWM signal outputting unit is configured to output a PWM signal, which is raised according to the start signal generated by itself and is decreased according to the termination signal generated by itself. Further, the PWM signal outputting units is configured to generate the termination signal when the counter value matches to the termination setting value generated by itself.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 10, 2015
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Kenjiro Matoba
  • Publication number: 20130069734
    Abstract: A PWM (Pulse Width Modulation) signal outputting circuit includes a counting unit for counting a number of clocks to output a counter value, and for resetting the counter value to resume counting when a reset signal is input to the counting unit; a dead time value storage unit for storing a dead time value; and a plurality of PWM signal outputting units for setting a start setting value and a termination setting value. The PWM signal outputting unit generates a termination signal and a start signal. Further, the PWM signal outputting unit is configured to output a PWM signal, which is raised according to the start signal generated by itself and is decreased according to the termination signal generated by itself. Further, the PWM signal outputting units is configured to generate the termination signal when the counter value matches to the termination setting value generated by itself.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 21, 2013
    Inventor: Kenjiro MATOBA
  • Patent number: 7366747
    Abstract: A digital filter circuit is capable of processing multi-channel data having different sampling frequencies. RAMs (random access memories) are provided which store data inputted thereto respectively, and the data outputted from the RAMs are alternately processed.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: April 29, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kenjiro Matoba
  • Patent number: 7334010
    Abstract: A digital filter includes a data storage section, a filter coefficient storage section, a multiplier, an accumulative adder section, a data output section and a control section. The data storage section stores the latest multiple input data for every channel and outputs the stored input data in response to a selection signal. The filter coefficient storage section stores predetermined filter coefficient corresponding to the multiple input data. The accumulative adder section adds the result of multiplication of multiple data from the multiplier for every channel. The data output section holds the result of addition in the accumulative adder section and outputting output data.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: February 19, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kenjiro Matoba
  • Patent number: 7324027
    Abstract: A circuit for testing an analog-digital converter includes: a subtracter which receives a converted value having a plurality of bits outputted from the analog-digital converter and an expected value having a plurality of bits, the subtracter calculating a difference value having a plurality of bits between the converted value and the expected value; and a logical operation circuit which receives the difference value, the logical operation circuit performing an exclusive-NOR operation between adjacent bits in the plurality of bits constituting the difference value, thereby outputting an exclusive-NOR value having a plurality of bits.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: January 29, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kenjiro Matoba