Abstract: An output circuit which has an improved protection circuit against an abnormal voltage applied to an output terminal. The output circuit is of the type having first and second switching transistors operating in a push-pull manner, the output being derived from the intermediate connection of the first and second switching transistor. A protection circuit is coupled between a gate of the first switching transistor and the output terminal. The protection circuit provides a current path between the gate of the first switching transistor and the output terminal when an abnormal voltage is applied to the output terminal.

Abstract: A memory circuit suitable for large scale integration is disclosed. The memory circuit comprises a plurality of memory cells each including a gate transistor having a gate coupled to one of word lines and a drain coupled to one of digit lines and capacitor means coupled between a source of the gate transistor and a potential source, wherein the threshold voltage of the gate transistors is made smaller than that of logic transistors employed in peripheral circuits.