Patents by Inventor Kenkichi Suezawa
Kenkichi Suezawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8338249Abstract: A method for manufacturing a semiconductor device comprises: forming a lower electrode on a semiconductor substrate, sputtering a ferroelectric film on the lower electrode using a target, thermal treating the ferroelectric film in an atmosphere containing oxygen in accordance with an accumulated period of use of the target for fabricating the ferroelectric film, and forming an upper electrode on the ferroelectric film.Type: GrantFiled: February 15, 2008Date of Patent: December 25, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Makoto Takahashi, Mitsushi Fujiki, Kenkichi Suezawa, Wensheng Wang, Ko Nakamura
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Publication number: 20100207178Abstract: A method for manufacturing a semiconductor device comprises: forming a lower electrode on a semiconductor substrate, sputtering a ferroelectric film on the lower electrode using a target, thermal treating the ferroelectric film in an atmosphere containing oxygen in accordance with an accumulated period of use of the target for fabricating the ferroelectric film, and forming an upper electrode on the ferroelectric film.Type: ApplicationFiled: February 15, 2008Publication date: August 19, 2010Applicant: FUJITSU LIMITEDInventors: Makoto TAKAHASHI, Mitsushi Fujiki, Kenkichi Suezawa, Wensheng Wang, Ko Nakamura
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Publication number: 20080070326Abstract: It is an aspect of the embodiments discussed herein to provide a method manufacturing a semiconductor device, including forming a bottom electrode film above a semiconductor substrate, forming an insulating film on the bottom electrode film, forming a top electrode on the insulating film, forming a capacitor insulating film by patterning the insulating film, and removing a substance adhered to at least one selected from a group consisting of the top electrode, the capacitor insulating film, the bottom electrode film by an etchback.Type: ApplicationFiled: September 18, 2007Publication date: March 20, 2008Applicant: FUJITSU LIMITEDInventor: Kenkichi SUEZAWA
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Publication number: 20080057598Abstract: A ferroelectric capacitor formation method that enables stable FeRAM mass production. When a ferroelectric capacitor of an FeRAM is formed, a ferroelectric layer is formed over a lower electrode layer by a sputtering method by keeping a stage at a temperature lower than or equal to 35° C. To crystallize the ferroelectric layer, first RTA treatment is performed in an atmosphere of a mixed gas which contains an inert gas and O2 gas a concentration of which is 1.25 volume percent or greater. The formation of an upper electrode layer, second RTA treatment, patterning, and the like are then performed to form the ferroelectric capacitor. By doing so, ferroelectric capacitors each having predetermined capacitor performance can be formed with a high yield and FeRAMs can stably be mass-produced.Type: ApplicationFiled: August 30, 2007Publication date: March 6, 2008Applicant: FUJITSU LIMITEDInventors: Kenkichi SUEZAWA, Mitsushi FUJIKI, Makoto TAKAHASHI, Ko NAKAMURA, Wensheng WANG
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Publication number: 20070122917Abstract: Disclosed is a ferroelectric capacitor forming method of allowing a FeRAM to be stably mass-produced. In forming the ferroelectric capacitor for the FeRAM, a PZT layer is formed on a lower electrode layer by a sputtering method. Then, a first RTA treatment for crystallizing the PZT is performed in an environment controlled such that predetermined capacitor performance such as a data holding property can be obtained regardless of the amount of a target previously used (used hours) in the sputtering method. For example, the O2 gas flow rate is controlled in an appropriate range during the first RTA treatment. Thereafter, formation of an upper electrode layer or a second RTA treatment is performed. As a result, the ferroelectric capacitor having predetermined capacitor performance can be formed with high yield, so that the FeRAM can be stably mass-produced.Type: ApplicationFiled: April 20, 2006Publication date: May 31, 2007Applicant: FUJITSU LIMITEDInventors: Mitsushi Fujiki, Kenkichi Suezawa, Makoto Takahashi, Ko Nakamura, Wensheng Wang
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Publication number: 20070114590Abstract: There are contained first and second conductive plugs formed in first insulating layer, an island-like oxygen-barrier metal layer for covering the first conductive plug, an oxidation-preventing insulating layer formed on the first insulating layer to cover side surfaces of the oxygen-barrier metal layer, a capacitor having a lower electrode formed on the oxygen-barrier metal layer and the oxidation-preventing insulating layer, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer, a second insulating layer for covering the capacitor and the oxidation-preventing insulating layer, a third hole formed in respective layers from the second insulating layer to the oxidation-preventing insulating layer on the second conductive plug, and a third conductive plug formed in the third hole and connected to the second conductive plug.Type: ApplicationFiled: January 10, 2007Publication date: May 24, 2007Applicant: FUJITSU LIMITEDInventors: Takashi Ando, Jiro Miura, Yukinobu Hirosaka, Akio Itoh, Junichi Watanabe, Kenkichi Suezawa
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Patent number: 7221015Abstract: There are contained first and second conductive plugs formed in first insulating layer, an island-like oxygen-barrier metal layer for covering the first conductive plug, an oxidation-preventing insulating layer formed on the first insulating layer to cover side surfaces of the oxygen-barrier metal layer, a capacitor having a lower electrode formed on the oxygen-barrier metal layer and the oxidation-preventing insulating layer, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer, a second insulating layer for covering the capacitor and the oxidation-preventing insulating layer, a third hole formed in respective layers from the second insulating layer to the oxidation-preventing insulating layer on the second conductive plug, and a third conductive plug formed in the third hole and connected to the second conductive plug.Type: GrantFiled: March 17, 2003Date of Patent: May 22, 2007Assignee: Fujitsu LimitedInventors: Takashi Ando, Jiro Miura, Yukinobu Hikosaka, Akio Itoh, Junichi Watanabe, Kenkichi Suezawa
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Patent number: 7139161Abstract: There are provides the steps of forming sequentially a first conductive film, a dielectric film, and a second conductive film on an insulating film, forming a first film on the second conductive film, forming a second film made of insulating material on the first film, forming hard masks by patterning the second film and the first film into a capacitor planar shape, etching the second conductive film and the dielectric film in a region not covered with the hard masks, etching the first conductive film in the region not covered with the hard masks up to a depth that does not expose the insulating film, removing the second film constituting the hard masks by etching, etching a remaining portion of the first conductive film in the region not covered with the hard masks to the end, and removing the first film.Type: GrantFiled: April 26, 2004Date of Patent: November 21, 2006Assignee: Fujitsu LimitedInventors: Genichi Komuro, Kenkichi Suezawa
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Publication number: 20040196618Abstract: There are provides the steps of forming sequentially a first conductive film, a dielectric film, and a second conductive film on an insulating film, forming a first film on the second conductive film, forming a second film made of insulating material on the first film, forming hard masks by patterning the second film and the first film into a capacitor planar shape, etching the second conductive film and the dielectric film in a region not covered with the hard masks, etching the first conductive film in the region not covered with the hard masks up to a depth that does not expose the insulating film, removing the second film constituting the hard masks by etching, etching a remaining portion of the first conductive film in the region not covered with the hard masks to the end, and removing the first film.Type: ApplicationFiled: April 26, 2004Publication date: October 7, 2004Applicant: FUJITSU LIMITEDInventors: Genichi Komuro, Kenkichi Suezawa
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Patent number: 6746878Abstract: There are provides the steps of forming sequentially a first conductive film, a dielectric film, and a second conductive film on an insulating film, forming a first film on the second conductive film, forming a second film made of insulating material on the first film, forming hard masks by patterning the second film and the first film into a capacitor planar shape, etching the second conductive film and the dielectric film in a region not covered with the hard masks, etching the first conductive film in the region not covered with the hard masks up to a depth that does not expose the insulating film, removing the second film constituting the hard masks by etching, etching a remaining portion of the first conductive film in the region not covered with the hard masks to the end, and removing the first film.Type: GrantFiled: January 29, 2003Date of Patent: June 8, 2004Assignee: Fujitsu LimitedInventors: Genichi Komuro, Kenkichi Suezawa
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Publication number: 20030227046Abstract: There are contained first and second conductive plugs formed in first insulating layer, an island-like oxygen-barrier metal layer for covering the first conductive plug, an oxidation-preventing insulating layer formed on the first insulating layer to cover side surfaces of the oxygen-barrier metal layer, a capacitor having a lower electrode formed on the oxygen-barrier metal layer and the oxidation-preventing insulating layer, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer, a second insulating layer for covering the capacitor and the oxidation-preventing insulating layer, a third hole formed in respective layers from the second insulating layer to the oxidation-preventing insulating layer on the second conductive plug, and a third conductive plug formed in the third hole and connected to the second conductive plug.Type: ApplicationFiled: March 17, 2003Publication date: December 11, 2003Inventors: Takashi Ando, Jiro Miura, Yukinobu Hikosaka, Akio Itoh, Junichi Watanabe, Kenkichi Suezawa
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Publication number: 20030173605Abstract: There are provides the steps of forming sequentially a first conductive film, a dielectric film, and a second conductive film on an insulating film, forming a first film on the second conductive film, forming a second film made of insulating material on the first film, forming hard masks by patterning the second film and the first film into a capacitor planar shape, etching the second conductive film and the dielectric film in a region not covered with the hard masks, etching the first conductive film in the region not covered with the hard masks up to a depth that does not expose the insulating film, removing the second film constituting the hard masks by etching, etching a remaining portion of the first conductive film in the region not covered with the hard masks to the end, and removing the first film.Type: ApplicationFiled: January 29, 2003Publication date: September 18, 2003Applicant: Fujitsu LimitedInventors: Genichi Komuro, Kenkichi Suezawa