Abstract: A thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate, is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer on the CMOS substrate is patterned by either undercut trenches extending into its upper surface or by T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.

Abstract: A thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate, is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer on the CMOS substrate is patterned by either undercut trenches extending into its upper surface or by T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.

Abstract: A method of forming a thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate so that the thin-film deposition is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer is formed on the CMOS substrate and is patterned by either forming undercut trenches extending into its upper surface or by fabricating T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.

Abstract: A wafer has a memory area and a logic area and a topmost metal contact layer on the surface covered with dielectric and etch stop layers. In the memory area, vias are opened through the dielectric and etch stop layers to topmost metal contact layer. In the logic area, evenly distributed dummy fill patterns are opened through a portion of the dielectric and etch stop layers. These are filled with a metal layer and planarized, forming a flat wafer surface. MTJ elements in the memory area and dummy elements in the logic area are formed on the flat surface. The dummy MTJ elements and fill patterns are etched away in the logic area. Metal connections are formed to the topmost metal contact layer in the logic area and top lead connections to MTJ elements are formed in the memory area.

Abstract: A magnetic thin film deposition is patterned and protected from oxidation during subsequent processes, such as bit line formation, by an oxidation-prevention encapsulation layer of SiN. The SiN layer is then itself protected during the processing by a metal overlayer, preferably of Ta, Al, TiN, TaN or W. A sequence of low pressure plasma etches, using Oxygen, Cl2, BCl3 and C2H4 chemistries provide selectivity of the metal overlayer to various oxide layers and to the photo-resist hard masks used in patterning and metal layer and thereby allow the formation of bit lines while maintaining the integrity of the SiN layer.

Abstract: A method of forming a thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate so that the thin-film deposition is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer is formed on the CMOS substrate and is patterned by either forming undercut trenches extending into its upper surface or by fabricating T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.

Abstract: An electrically programmable, non-volatile resistive memory includes an array of memory cells, a plurality of bit lines, and a plurality of word lines. Each memory cell comprises a resistive element and a Schottky diode coupled in series and having first and second terminals. Each bit line couples to the first terminal of all memory cells in a respective column of the array. Each word line couples to the second terminal of all memory cells in a respective row of the array. The resistive element for each memory cell may be formed with a film of a perovskite material (e.g., Pr0.7Ca0.3MnO3). The Schottky diode for each memory cell may be formed by a thin film of amorphous silicon. The films for the resistive element and Schottky diode for each memory cell may be stacked in a compact island at the cross point between a bit line and a word line.

Abstract: A method of manufacturing a non-volatile semiconductor memory. The method includes forming a word gate poly layer on a substrate, wherein an upper surface of the substrate defines a plane of the substrate. The method also includes forming a first dielectric layer coupled to the word gate poly layer and patterning the word gate poly layer and the first dielectric layer to form an array of word gate structures. The method further includes forming a poly plug layer and patterning the poly plug layer to form a plurality of poly plugs surrounded in the plane of the substrate on three sides, forming a plurality of control gates, forming a second dielectric layer, planarizing the second dielectric layer using a chemical-mechanical polishing process, and depositing a metal layer to provide electrical contact to the word gate structures.

Abstract: A high selectivity and etch rate with innovative approach of inductively coupled plasma source. Preferably, the invention includes a method using plasma chemistry that is divided into main etch step of (e.g., Cl2+HBr+C4F8) gas combination and over etch step of (e.g., HBr+Ar). The main etch step provides a faster etch rate and selectivity while the over etch step will decrease the etch rate and ensure the stringer and residue removal without attacking the under layer.

Abstract: An MONOS integrated circuit device. The device has a semiconductor substrate comprising a silicon bearing material and a shallow trench isolation region formed within the substrate. A P-type well region is formed within the substrate and adjacent to the shallow trench isolation region. The first word gate comprising a first edge and a second edge. The first word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. Preferably, the second word gate comprises a first edge and a second edge. The second word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. A common buried bit line is formed within the P-type well region and between the second edge of the first word gate and the first edge of the second word gate.

Abstract: An MONOS integrated circuit device. The device has a semiconductor substrate comprising a silicon bearing material and a shallow trench isolation region formed within the substrate. A P-type well region is formed within the substrate and adjacent to the shallow trench isolation region. The first word gate comprising a first edge and a second edge. The first word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. Preferably, the second word gate comprises a first edge and a second edge. The second word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. A common buried bit line is formed within the P-type well region and between the second edge of the first word gate and the first edge of the second word gate.

Abstract: A high selectivity and etch rate with innovative approach of inductively coupled plasma source. Preferably, the invention includes a method using plasma chemistry that is divided into main etch step of (e.g., Cl2+HBr+C4F8) gas combination and over etch step of (e.g., HBr+Ar). The main etch step provides a faster etch rate and selectivity while the over etch step will decrease the etch rate and ensure the stringer and residue removal without attacking the under layer.

Abstract: One embodiment of the present invention is a method used to fabricate a device on a substrate, which method is utilized at a stage of processing wherein a metal gate stack is disposed or formed over a gate oxide, which metal stack includes a refractory metal layer disposed or formed over a refractory metal barrier/adhesion layer, which method includes steps of: (a) etching the refractory metal layer and stopping on or in the refractory metal barrier/adhesion layer; and (b) etching the refractory metal barrier/adhesion layer using a passivation etching chemistry without oxygen.

Abstract: A method of eliminating charging resulting from plasma processing a semiconductor wafer comprising the steps of plasma processing the semiconductor wafer in a manner that may result in topographically dependent charging and exposing, during at least a portion of a time in which the semiconductor wafer is being plasma processed, the semiconductor wafer to particles that remove charge from the semiconductor wafer and reduce topographically dependent charging.

Abstract: One embodiment of the present invention is a method used to fabricate a device on a substrate, which method is utilized at a stage of processing wherein a metal gate stack is disposed or formed over a gate oxide, which metal stack includes a refractory metal layer disposed or formed over a refractory metal barrier/adhesion layer, which method includes steps of: (a) etching the refractory metal layer and stopping on or in the refractory metal barrier/adhesion layer; and (b) etching the refractory metal barrier/adhesion layer using a passivation etching chemistry without oxygen.