Patents by Inventor Kenneth A. BATES

Kenneth A. BATES has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process of forming an electronic device including a non-volatile memory cell
    Patent number: 11545583
    Abstract: An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: January 3, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Weize Chen, Sameer S. Haddad, Bruce B. Greenwood, Mark Griswold, Kenneth A. Bates
  • Electronic Device Including a Non-Volatile Memory Cell and a Process of Forming the Same
    Publication number: 20220254920
    Abstract: An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.
    Type: Application
    Filed: February 5, 2021
    Publication date: August 11, 2022
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Weize Chen, Sameer S. Haddad, Bruce B. Greenwood, Mark Griswold, Kenneth A. Bates
  • Siloxane and organic-based MOL contact patterning
    Patent number: 10056458
    Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chang Ho Maeng, Andy Wei, Anthony Ozzello, Bharat Krishnan, Guillaume Bouche, Haifeng Sheng, Haigou Huang, Huang Liu, Huy M. Cao, Ja-Hyung Han, SangWoo Lim, Kenneth A. Bates, Shyam Pal, Xintuo Dai, Jinping Liu
  • SILOXANE AND ORGANIC-BASED MOL CONTACT PATTERNING
    Publication number: 20170200792
    Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 13, 2017
    Inventors: Chang Ho MAENG, Andy WEI, Anthony OZZELLO, Bharat KRISHNAN, Guillaume BOUCHE, Haifeng SHENG, Haigou HUANG, Huang LIU, Huy M. CAO, Ja-Hyung HAN, SangWoo LIM, Kenneth A. BATES, Shyam PAL, Xintuo DAI, Jinping LIU