Abstract: A floating-point processor nominally capable of single and double, but not extended, precision execution stores operands in extended-precision format. A format converter converts single and double precision source values to extended-precision format. Trap logic checks the apparent precision of the extended-precision operands and the requested result precision to determine whether the floating-point processor can execute the requested operation and yield the appropriate result. If the maximum of the requested precision and the maximum apparent precision of the operands is single or double, the requested operation is executed in hardware. Otherwise, a trap is issued to call an extended precision floating-point subroutine. This approach augments the class of operations that can be handled in hardware by a double-precision floating-point processor, and thus improves the floating-point computational throughput of an incorporating computer system.

Abstract: A microprocessor includes a programmable instruction trap that can be used to deimplement instructions that lead to erroneous results. Upon discovery of a logic design defect, a microprocessor manufacturer can distribute an updated exception handler and a patch for a boot sequence. Upon power up, the boot sequence programs instructions to be deimplemented into a trap list. Each received instruction (issued by an application program, for example) not matching any listed instruction is executed in due course. When it matches a listed deimplemented instruction, the received instruction is trapped: it is not executed but is stored in a dedicated register. An exception handler is called that can examine the trapped instruction and substitute a suitable routine. If the trapped instruction is conditionally deimplemented and the problematic conditions do not pertain, the exception handler can reissue the instruction after temporarily deactivating the trapping function.

Abstract: A method in accordance with the present invention for developing an integrated circuit design using a compilation tool includes: (A) developing at least one HDL template by: (a) creating the HDL template; (b) creating a parameter file and a parameter check file for the HDL template; and (c) encrypting the HDL template; (B) developing design specifications for use in creating HDL for synthesis and for use in compiling one or more macro blocks; (C) creating the HDL for synthesis; and (D) creating netlists for at least one macro block instantiated in the HDL template using the design specifications. A development tool of the present invention implements the method on a computer system to form a portion of an integrated circuit fabrication system.

Abstract: A data processing system includes a microprocessor, memory, and an instruction substitution filter. The microprocessor has separate data and instruction caches. The filter includes configuration memory that occupies memory mapped I/O space. Configuration data indicating instruction types to be deimplemented is entered into the filter during a boot sequence. Once configured, the filter substitutes call instructions for the deimplemented instructions. When executed, the call instructions activate a substitution routine that determines the address of the deimplemented instruction and then performs a data read of the unfiltered deimplemented instructions and then implements the function that the deimplemented function was intended to implement (but, due to microprocessor defects, does not). Accordingly, the present invention allows a microprocessor with defectively implemented instructions to be used as intended with minimal performance penalties.

Abstract: A packet-data FIFO buffer system comprises a FIFO buffer with a series of FIFO memory locations. Each FIFO memory location includes a data section for storing a packet data word and a flag section for storing an indication of whether or not the associated data section includes the last word of a packet. The FIFO buffer capacity is not limited to the number of maximum length packets it can hold; instead, a greater number of small packets can be stored. This increases the effectiveness of available FIFO memory and minimizes communication delays along the channels serviced by the FIFO. The FIFO design is simple and fairly self contained so that minimal external logic and control is required. In addition, an indication of the presence or absence of a complete data packet in the FIFO buffer can be easily obtained by logically adding (ORing) the contents of the flag sections.

Abstract: A method for designing a constant multiplier system comprises identifying a repeated pattern in a minimal signed digit expression of a multiplier, designing a first accumulator stage to compute the product of a multiplicand by an instance of the pattern, and designing a second accumulator stage for accumulating shifted replicas of the pattern to yield a final product. Remainder terms, for example corresponding to non-zero digit positions not included in any instance of the pattern, are also accumulated at the second stage. By limiting the method to patterns with at least two non-zero values, the result tends to reduce the number of operations that must be performed to determine a final product. Thus, the size, complexity and speed of a constant multiplier system can be optimized.

Abstract: A constant multiplication device is designed for multiplying a received binary multiplicand by a constant multiplier which, when expressed in binary or signed-digit notation, includes a repeated pattern with three or more non-zero values. The device includes a pattern-product term generator that receives the multiplicand and generates terms corresponding to each of the non-zero values of the pattern. If, when all instances of the pattern are subtracted from the multiplier there are non-zero values in the difference, the pattern-product term generator can also generate remainder-product terms. The pattern-product terms, but not the remainder-product terms, are input to a pattern compressor that yields pattern-product partials; the compressor can be a carry-save adder and the partials can be in the form of a pseudo sum and a pseudo carry. A replica generator generates shifted replicas of each pattern-product partial. The replicas are input to a replica compressor, as are any remainder-product terms.

Abstract: A zero-run-length encoder for a JPEG compression system comprises an addressable memory for storing 63 input values (quantized AC DCT coefficients), zero-detection logic, a shift register, a value generator, an accumulator, a Huffman encoder, done-detection logic, and last-value-detection logic. For each input value, the zero-detection logic stores zero/nonzero indications in a respective bit position of the shift register. The value generator includes a leading-zero counter that determines the number of leading zeroes in the leading fifteen bit positions of the shift register. This count is used to determine an offset value which is added to a previous address value (initially zero) to yield a present address value. The present address value is used to select a memory location from which an input value is read from memory into the Huffman encoder. The Huffman encoder generates an output code as a function of the addressed input value and the leading zero count.

Abstract: A hybrid Harvard/Von Neumann data processing system utilizes a Harvard architecture processor with a combined data/instruction memory. A dual-port random-access instruction buffer between memory and the processor provides much of the performance enhancement of an instruction cache when used with a RISC instruction set, but at a much lower cost. The resulting system serves as an entry-level computer system of a series of compatible computers, led at the high end by a Harvard processor with full data and instruction caches.

Abstract: A microprocessor provides for a single-cycle and a dual-cycle instruction mode. In the single-cycle mode, certain instructions, e.g., a "shift plus add" instruction, are performed in a single cycle with a relatively low clock rate. In the dual-cycle mode, the shift is performed in the first cycle and the add is performed in the second cycle with a relatively high clock rate. In the dual-cycle mode, a cycle can be dropped if the shift amount is zero or one of the operands is zero. A system designer and/or a programmer can select the mode to maximize throughput.

Abstract: A data processor includes 32 user registers arranged in two banks of 16 registers each. 4-bit addressing is provided. A 16-bit map register determines the bank from which an addressed register is selected. This determination is made individually for each address. The map register is readable and writable so that the mapping of addresses to banks is under program control. This arrangement provides for accessing a large number of registers using a short address code; registers remaining addressable after a remapping retain their addresses.

Abstract: An arithmetic logic unit provides for zero-result prediction so as to eliminate the latency between successive operations (e.g., multiplication and division) when a zero detection is a condition for performance of the second operation. Instead of performing zero detection on the result, zero prediction is performed on the initial or intermediate operands, (e.g., partial products that are summed to generate a product). To this end, zero-prediction logic determines whether or not both of the following conditions are met: 1) either the least significant bits of the addends are the same and the carry-in is zero or the least significant bits of the addends are different and the carry-in is one. 2) for each pair of adjacent bit positions, the four included bits are consistent with addend complementarity. If both conditions are met, a zero result is predicted; otherwise, a non-zero result is predicted.

Abstract: A Harvard architecture data processing system includes a processor, main memory, an instruction cache, and a data cache. As is generally known with the Harvard architecture, these components are interconnected by an instruction bus, an instruction address bus, a data bus, and a data address bus. The instruction cache includes a branch target section and a general instruction section. For each instruction request by the processor, both sections are examined to determine if the requested instruction is in the cache. If it is, it is transmitted from the cache to the processor. If it is not, an instruction line including the requested instruction is fetched from main memory. If the requested instruction represents a jump (the result of an unconditional branch or a conditional branch the condition of which is met) the fetched instruction line can be stored only in the branch target section.

Abstract: An arithmetic logic unit provides for zero-result prediction so as to eliminate the latency between successive operations (e.g., multiplication and division) when a zero detection is a condition for performance of the second operation. Instead of performing zero detection on the result, zero prediction is performed on the initial or intermediate operands, (e.g., partial products that are summed to generate a product). To this end, zero-prediction logic determines whether or not both of the following conditions are met: 1) either the least significant bits of the addends are the same and the carry-in is zero or the least significant bits of the addends are different and the carry-in is one. 2) for each pair of adjacent bit positions, the four included bits are consistent with addend complementarity. If both conditions are met, a zero result is predicted; otherwise, a non-zero result is predicted.

Abstract: A floating-point processor comprises an input format converter, operand registers, a mode selector, an execution unit, and a result format converter. Inputs to the processor include first and second source values, low and high order result precision selectors, and an operation selector. The input format converter converts the source values to extended precision operands for storage in the registers. The mode selector is responsive to the apparent precisions, i.e., the numbers of trailing zeroes in the mantissas, of the operands as well as to the requested precision. The maximum of the requested result precision and the apparent precision determines the precision implemented by the execution unit. The results are stored in extended precision regardless of the execution precision. If the requested precision is less than extended, the result format converter converts the result to the requested format.