Patents by Inventor Kenneth A. Gerber

Kenneth A. Gerber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of construction of CTE matching structure with wafer processing and resulting structure
    Patent number: 8084288
    Abstract: A method includes bonding a first side of a metal shim to a silicon shim, removing metal from the metal shim to form a plurality of cleared metal lanes in accordance with a pattern, bonding a readout integrated circuit having a plurality of saw lanes in accordance with the pattern to a second side of the metal shim to form a wafer assembly wherein the plurality of saw lanes is aligned with the plurality of cleared metal lanes, and dicing the wafer assembly.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: December 27, 2011
    Assignee: Raytheon Company
    Inventors: Robert P. Ginn, Kenneth A. Gerber
  • Method of construction of CTE matching structure with wafer processing and resulting structure
    Publication number: 20100001188
    Abstract: A method includes bonding a first side of a metal shim to a silicon shim, removing metal from the metal shim to form a plurality of cleared metal lanes in accordance with a pattern, bonding a readout integrated circuit having a plurality of saw lanes in accordance with the pattern to a second side of the metal shim to form a wafer assembly wherein the plurality of saw lanes is aligned with the plurality of cleared metal lanes, and dicing the wafer assembly.
    Type: Application
    Filed: August 11, 2009
    Publication date: January 7, 2010
    Inventors: Robert P. Ginn, Kenneth A. Gerber
  • Method of construction of CTE matching structure with wafer processing and resulting structure
    Patent number: 7592594
    Abstract: A method includes bonding a first side of a metal shim to a silicon shim, removing metal from the metal shim to form a plurality of cleared metal lanes in accordance with a pattern, bonding a readout integrated circuit having a plurality of saw lanes in accordance with the pattern to a second side of the metal shim to form a wafer assembly wherein the plurality of saw lanes is aligned with the plurality of cleared metal lanes, and dicing the wafer assembly.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: September 22, 2009
    Assignee: Raytheon Company
    Inventors: Robert P. Ginn, Kenneth A. Gerber
  • Infrared photodiodes and sensor arrays with improved passivation layers and methods of manufacture
    Patent number: 7544532
    Abstract: InSb infrared photodiodes and sensor arrays with improved passivation layers and methods for making same are disclosed. In the method, a passivation layer of AlInSb is deposited on an n-type InSb substrate using molecular beam epitaxy before photodiode detector regions are formed in the n-type substrate. Then, a suitable P+ dopant is implanted directly through the AlInSb passivation layer to form photodiode detector regions. Next, the AlInSb passivation layer is selectively removed, exposing first regions of the InSb substrate, and gate contacts are formed in the first regions of the InSb substrate. Then, additional portions of the AlInSb passivation layer are selectively removed above the photodiode detectors exposing second regions. Next, metal contacts are formed in the second regions, and bump contacts are formed atop the metal contacts. Then, an antireflection coating is applied to a side of the substrate opposite from the side having the metal and bump contacts.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: June 9, 2009
    Assignee: Raytheon Company
    Inventors: Robert P. Ginn, Kenneth A. Gerber, Andreas Hampp, Alexander C. Childs
  • Method of construction of CTE matching structure with wafer processing and resulting structure
    Publication number: 20080113495
    Abstract: A method includes bonding a first side of a metal shim to a silicon shim, removing metal from the metal shim to form a plurality of cleared metal lanes in accordance with a pattern, bonding a readout integrated circuit having a plurality of saw lanes in accordance with the pattern to a second side of the metal shim to form a wafer assembly wherein the plurality of saw lanes is aligned with the plurality of cleared metal lanes, and dicing the wafer assembly.
    Type: Application
    Filed: November 13, 2006
    Publication date: May 15, 2008
    Inventors: Robert P. Ginn, Kenneth A. Gerber
  • Infrared photodiodes and sensor arrays with improved passivation layers and methods of manufacture
    Publication number: 20080090319
    Abstract: InSb infrared photodiodes and sensor arrays with improved passivation layers and methods for making same are disclosed. In the method, a passivation layer of AlInSb is deposited on an n-type InSb substrate using molecular beam epitaxy before photodiode detector regions are formed in the n-type substrate. Then, a suitable P+ dopant is implanted directly through the AlInSb passivation layer to form photodiode detector regions. Next, the AlInSb passivation layer is selectively removed, exposing first regions of the InSb substrate, and gate contacts are formed in the first regions of the InSb substrate. Then, additional portions of the AlInSb passivation layer are selectively removed above the photodiode detectors exposing second regions. Next, metal contacts are formed in the second regions, and bump contacts are formed atop the metal contacts. Then, an antireflection coating is applied to a side of the substrate opposite from the side having the metal and bump contacts.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 17, 2008
    Inventors: Robert Ginn, Kenneth Gerber, Andreas Hampp, Alexander Childs