Abstract: Multiple clients may attempt to utilize a coprocessor engine within a coprocessor simultaneously. However, each engine may accomplish the particular function for which it is designed for one client at a time. Therefore, to transition from performing coprocessor engine operations between clients, the coprocessor engine may be suspended from performing operations for a first client so that it may begin performing operations for a second client. Prior to such transition, the coprocessor engine saves metadata about its operation state at the time of the suspension. At a subsequent time, when operations for the first client are to resume, the operating state of the coprocessor engine is determined utilizing the metadata and operations for the first client resume.

Abstract: Multiple clients may attempt to utilize a coprocessor engine within a coprocessor simultaneously. However, each engine may accomplish the particular function for which it is designed for one client at a time. Therefore, to transition from performing coprocessor engine operations between clients, the coprocessor engine may be suspended from performing operations for a first client so that it may begin performing operations for a second client. Prior to such transition, the coprocessor engine saves metadata about its operation state at the time of the suspension. At a subsequent time, when operations for the first client are to resume, the operating state of the coprocessor engine is determined utilizing the metadata and operations for the first client resume.

Abstract: Multiple clients may attempt to utilize a coprocessor engine within a coprocessor simultaneously. However, each engine may accomplish the particular function for which it is designed for one client at a time. Therefore, to transition from performing coprocessor engine operations between clients, the coprocessor engine may be suspended from performing operations for a first client so that it may begin performing operations for a second client. Prior to such transition, the coprocessor engine saves metadata about its operation state at the time of the suspend. At a subsequent time, when operations for the first client are to resume, the operating state of the coprocessor engine is determined utilizing the metadata and operations for the first client resume.

Abstract: Multiple clients may attempt to utilize a coprocessor engine within a coprocessor simultaneously. However, each engine may accomplish the particular function for which it is designed for one client at a time. Therefore, to transition from performing coprocessor engine operations between clients, the coprocessor engine may be suspended from performing operations for a first client so that it may begin performing operations for a second client. Prior to such transition, the coprocessor engine saves metadata about its operation state at the time of the suspend. At a subsequent time, when operations for the first client are to resume, the operating state of the coprocessor engine is determined utilizing the metadata and operations for the first client resume.

Abstract: According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.

Abstract: According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.

Abstract: Multiple clients may attempt to utilize a coprocessor engine within a coprocessor simultaneously. However, each engine may accomplish the particular function for which it is designed for one client at a time. Therefore, to transition from performing coprocessor engine operations between clients, the coprocessor engine may be suspended from performing operations for a first client so that it may begin performing operations for a second client. Prior to such transition, the coprocessor engine saves metadata about its operation state at the time of the suspend. At a subsequent time, when operations for the first client are to resume, the operating state of the coprocessor engine is determined utilizing the metadata and operations for the first client resume.

Abstract: Multiple clients may attempt to utilize a coprocessor engine within a coprocessor simultaneously. However, each engine may accomplish the particular function for which it is designed for one client at a time. Therefore, to transition from performing coprocessor engine operations between clients, the coprocessor engine may be suspended from performing operations for a first client so that it may begin performing operations for a second client. Prior to such transition, the coprocessor engine saves metadata about its operation state at the time of the suspend. At a subsequent time, when operations for the first client are to resume, the operating state of the coprocessor engine is determined utilizing the metadata and operations for the first client resume.

Abstract: According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.

Abstract: According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.

Abstract: A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system tracks delivery of data to destinations in the primary coherent system via one or more entries in a data structure. Each of the one or more entries specifies with a destination tag a destination in the primary coherent system to which data is to be delivered from the attached processor. In response to initiation of recovery operations for the CAPP, the CAPP performs data recovery operations, including transmitting, to at least one destination indicated by the destination tag of one or more entries, an indication of a data error in data to be delivered to that destination from the attached processor.

Abstract: A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system tracks delivery of data to destinations in the primary coherent system via one or more entries in a data structure. Each of the one or more entries specifies with a destination tag a destination in the primary coherent system to which data is to be delivered from the attached processor. In response to initiation of recovery operations for the CAPP, the CAPP performs data recovery operations, including transmitting, to at least one destination indicated by the destination tag of one or more entries, an indication of a data error in data to be delivered to that destination from the attached processor.

Abstract: A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system tracks delivery of data to destinations in the primary coherent system via one or more entries in a data structure. Each of the one or more entries specifies with a destination tag a destination in the primary coherent system to which data is to be delivered from the attached processor. In response to initiation of recovery operations for the CAPP, the CAPP performs data recovery operations, including transmitting, to at least one destination indicated by the destination tag of one or more entries, an indication of a data error in data to be delivered to that destination from the attached processor.

Abstract: A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system tracks delivery of data to destinations in the primary coherent system via one or more entries in a data structure. Each of the one or more entries specifies with a destination tag a destination in the primary coherent system to which data is to be delivered from the attached processor. In response to initiation of recovery operations for the CAPP, the CAPP performs data recovery operations, including transmitting, to at least one destination indicated by the destination tag of one or more entries, an indication of a data error in data to be delivered to that destination from the attached processor.

Abstract: A cache for use in a central processing unit (CPU) of a computer includes a data array; a tag array configured to hold a list of addresses corresponding to each data entry held in the data array; a least recently used (LRU) array configured to hold data indicating least recently used data entries in the data array; a line fill buffer configured to receive data from an address in main memory that is located external to the cache in the event of a cache miss; and a shadow register associated with the line fill buffer, wherein the shadow register is configured to hold LRU data indicating a current state of the LRU array.

Abstract: A cache for use in a central processing unit (CPU) of a computer includes a data array; a tag array configured to hold a list of addresses corresponding to each data entry held in the data array; a least recently used (LRU) array configured to hold data indicating least recently used data entries in the data array; a line fill buffer configured to receive data from an address in main memory that is located external to the cache in the event of a cache miss; and a shadow register associated with the line fill buffer, wherein the shadow register is configured to hold LRU data indicating a current state of the LRU array.

Abstract: A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures.

Abstract: A chip design methodology and an integrated circuit chip. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).

Abstract: A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).

Abstract: A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures.