Abstract: An improved communication system, receiver, and method are provided that can reduce input voltages received by the receiver whenever those voltages extend upward to the maximum common-mode voltage range. A detect circuit determines whether the input voltages are at or near the maximum range. If so, the detect circuit sends a control signal to a level shift circuit which will reduce the input voltages by a predefined amount. The reduced voltages can then be forwarded to a sense circuit which preferably operates at a power supply voltage that is less than the maximum differential input voltage (i.e., the maximum voltage on the differential pair of signals), or less than the maximum common-mode voltage of the differential input signals. The sense circuit can thereby operate at a relatively wide common-mode voltage range, and utilizes a lower power supply voltage.

Abstract: An apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output signals are generally each at either (i) the same logic state or (ii), a don't care state.

Abstract: An apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output signals are generally each at either (i) the same logic state or (ii) a high-Z state.