Patents by Inventor Kenneth A. Mahler
Kenneth A. Mahler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7729877Abstract: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.Type: GrantFiled: October 31, 2007Date of Patent: June 1, 2010Assignee: International Business Machines CorporationInventors: Robert J. Devins, Paul J. Ferro, Peter D. LaFauci, Kenneth A. Mahler, David W. Milton
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Publication number: 20080222583Abstract: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.Type: ApplicationFiled: October 31, 2007Publication date: September 11, 2008Applicant: International Business Machines CorporationInventors: Robert J. Devins, Paul J. Ferro, Peter D. LaFauci, Kenneth A. Mahler, David W. Milton
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Patent number: 7353131Abstract: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.Type: GrantFiled: November 15, 2004Date of Patent: April 1, 2008Assignee: International Business Machines CorporationInventors: Robert J. Devins, Paul J. Ferro, Peter D. LaFauci, Kenneth A. Mahler, David W. Milton
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Publication number: 20070204246Abstract: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.Type: ApplicationFiled: May 4, 2007Publication date: August 30, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert Devins, Paul Ferro, Peter LaFauci, Kenneth Mahler, David Milton
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Publication number: 20050144577Abstract: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.Type: ApplicationFiled: November 15, 2004Publication date: June 30, 2005Applicant: International Business MachinesInventors: Robert Devins, Paul Ferro, Peter LaFauci, Kenneth Mahler, David Milton
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Patent number: 6868545Abstract: The time, effort and expense required to develop verification software for testing and de-bugging system-on-chip (SOC) designs represents a considerable investment. According to the method of the present invention, a portion of such verification software may be re-used in an operating system (OS) (i.e., a system used for, e.g., general business, technical or scientific applications as opposed to software testing) to capitalize on the investment. The verification software includes low-level device drivers (LLDDs) which were coded for and paired with specific device designs (“cores”) throughout the verification process, and were consequently also verified (i.e., de-bugged) in the process. Thus, the low-level device drivers represent reliable software with detailed knowledge of the corresponding devices.Type: GrantFiled: January 31, 2000Date of Patent: March 15, 2005Assignee: International Business Machines CorporationInventors: Robert J. Devins, Paul G. Ferro, Robert D. Herzl, Kenneth A. Mahler
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Patent number: 6865502Abstract: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.Type: GrantFiled: April 4, 2001Date of Patent: March 8, 2005Assignee: International Business Machines CorporationInventors: Robert J. Devins, Paul J. Ferro, Peter D. LaFauci, Kenneth A. Mahler, David W. Milton
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Patent number: 6571373Abstract: A method for communicating with and controlling design logic modules (“cores”) external to a system-on-chip (SOC) design during verification of the design uses verification software to generate and apply test cases to stimulate components of an SOC design in simulation; the results are observed and used to de-bug the design. Typically, SOC designs interface with cores that are external to the design. Existing methods of including such external cores in a verification test of a SOC design typically entail having to create special test cases to control the external cores; such test cases typically do not communicate with test cases being applied internally to the SOC and therefore lack realism. An external memory-mapped test device (EMMTD) according to the present invention is coupled between a SOC design being tested in simulation, and cores external to the SOC design.Type: GrantFiled: January 31, 2000Date of Patent: May 27, 2003Assignee: International Business Machines CorporationInventors: Robert J. Devins, Mark E. Kautzman, Kenneth A. Mahler, William E. Mitchell
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Patent number: 6539522Abstract: A method for developing re-usable software for the efficient verification of system-on-chip (SOC) integrated circuit designs. The verification software is used to generate and apply test cases to stimulate components of a SOC design (“cores”) in simulation; the results are observed and used to de-bug the design. The software is hierarchical, implementing a partition between upper-level test application code which generates test cases and verifies results, and low-level device driver code which interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations. Test application and supporting low-level device driver pairs are used and re-used to test their corresponding component cores throughout the SOC development process, by creating higher-level test control programs which control selected combinations of the already-developed test application and device driver programs to test combinations of SOC components.Type: GrantFiled: January 31, 2000Date of Patent: March 25, 2003Assignee: International Business Machines CorporationInventors: Robert J. Devins, Paul G. Ferro, Robert D. Herzl, Mark E. Kautzman, Kenneth A. Mahler, David W. Milton
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Publication number: 20020147560Abstract: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.Type: ApplicationFiled: April 4, 2001Publication date: October 10, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert J. Devins, Paul J. Ferro, Peter D. LaFauci, Kenneth A. Mahler, David W. Milton
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Patent number: 6427224Abstract: A method for using verification software for testing a system-on-chip (SOC) design including an embedded processor. The verification software is used to generate and apply test cases to stimulate the SOC design in simulation; the results are observed and used to de-bug the design. Verification of a SOC design which includes an embedded processor is typically very slow. To provide for a speed-up mode of verification in such a case, in the method of the present invention, verification software is partitioned into higher-level control code and lower-level device driver code. The higher-level code performs such functions as decision-making, test initialization, test randomization, multi-tasking, and comparison of test results with expected results. The low-level code interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations.Type: GrantFiled: January 31, 2000Date of Patent: July 30, 2002Assignee: International Business Machines CorporationInventors: Robert J. Devins, Mark E. Kautzman, Kenneth A. Mahler, David W. Milton
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Patent number: D259497Type: GrantFiled: March 16, 1979Date of Patent: June 9, 1981Assignee: The Sunfloat CompanyInventor: Kenneth Mahler
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Patent number: D349146Type: GrantFiled: October 4, 1993Date of Patent: July 26, 1994Inventor: Kenneth Mahler