Abstract: A structure for a system of chip packages includes a master substrate and at least one subset substrate of the master substrate. The subset substrate includes a portion of the master substrate that has an identical pin out pattern as the portion of the master substrate. The subset substrate has identical internal net lists as the portion of the master substrate. The subset substrate is adapted to accommodate a smaller chip than the master substrate. The master substrate is the largest substrate in the system. The invention also prepares a system of chip packages. The invention selects a master substrate and then selects a subset substrate of the master substrate.

Abstract: A method, system and program product implementing storage of a (power or ground) mesh plane file using a multiple line shape, possibly with the storage of lines also, to reduce file size. In addition, the invention implements an activate-substantial-portion-and-remove technique to generate mesh planes rather than the conventional additive approach, which improves the speed of designing the IC carriers. A resulting mesh plane design file may be as much as half the size of a file generated using the conventional line-by-line and storage approaches.