Abstract: A hand tool grinding jig is described for use in co-operation with a grinding wheel. The jig has a tool clamp for clamping a hand tool and a leg is pivotally connected to the clamp to allow the angle between the leg and the clamp to be adjusted. An end of the leg remote from the clamp provides a pivot point for engagement in a pivot receiver of a pivot support member that is located adjacent to the grinding wheel. The pivot receiver is disposed so that, when a tool is in the tool clamp and the pivot point is provided in the pivot receiver, the pivotal axis between the leg and the clamp is further from the grinding wheel than the pivot receiver.

Abstract: Semiconductor devices 340 are formed in semiconductor wafer 300. Contact pads 332 are formed in each die 330. An interconnect connects the contact pads 332 to die surface contact regions 210, 212. Scribe trenches 348 are formed in device wafer 300; corresponding trenches 358 are formed in cover wafer 360. The cover wafer 360 is thinned to open scribe trenches 348. Conductive vias 310-313 connect the contact pads 210, 212 to external surface bump contacts 333.

Abstract: Semiconductor devices 340 are formed in semiconductor wafer 300. Contact pads 332 are formed in each die 330. An interconnect connects the contact pads 332 to die surface contact regions 210, 212. Scribe trenches 348 are formed in device wafer 300; corresponding trenches 358 are formed in cover wafer 360. The cover wafer 360 is thinned to open scribe trenches 348. Conductive vias 310-313 connect the contact pads 210, 212 to external surface bump contacts 333.

Abstract: Interconnect metal is selectively provided in a network of trenches formed in the top surface of a semiconductor substrate containing multiple circuit devices, electrical contact to regions of which is to be provided. The trench network is formed so that it intersects the device regions, thus exposing the regions at sidewalls of the trench. On the floor of the trench a bottom layer of insulator material is provided, and conductive material (such as tungsten) is deposited on or grown from the trench sidewalls, in order to electrically couple device regions to one another. Because the device interconnect employs a trench network, not only are top surface contact apertures unnecessary, but, with a device region contact (from the trench sidewall) being made along the entire width of the region, device resistance can be decreased and performance improved.

Abstract: The numerical position relative to a reference indicia of two most nearly aligned overlapping indicia on two separate levels is multiplied by the difference in spacing of the indicia of the patterns on the two levels to determine the degree of misalignment of the levels.

Abstract: A thermal oxide is grown on a semiconductor substrate containing single crystal, dielectrically isolated tubs. A silicon nitride layer, serving as a mask for complete self-alignment of collector contacts, bases and emitters is then deposited. After the silicon nitride is patterned, the wafer is reoxidized. The oxide over the emitter and collector contact areas is then etched using the previously patterned silicon nitride film as an alignment mask. The remaining silicon nitride is stripped, a base photoresist pattern is formed and a base impurity ion implant is performed, to define the essential profile of the base. Polysilicon is then deposited and implanted with impurities to form 4000 ohm/square resistors. Silicon dioxide is deposited over the areas of polysilicon which are to become resistors when the polysilicon is patterned, which silicon dioxide masks the polysilicon resistor precursors from the impurities implant conducted for the collector contact, emitter and interconnects.

Abstract: The dice of a wafer are serialized using a wafer mask formed by stepping and repeating a chip pattern with a blank area in rows and columns on the wafer and forming distinctive location identifying indicia in the blank area on each chip using a pattern generator and stepping to each blank area on each chip.

Abstract: A memory cell having two mesa bipolar transistors separated by a valley in which two doped polycrystalline load resistors are formed. Doped polycrystalline conductors connect the resistors to a respective backside metallic collector contact which is between a support structure and a transistor and to a respective base.The cell is fabricated by removing a substrate upon which was formed an epitaxial layer and top support, applying a backside metallic layer, forming a bottom support, removing the top support, etching the epitaxial layer to form mesas, etching the backside metal to form discrete contacts, and forming multi-level resistors and conductors in the valley between the mesa transistors separated by insulative material.

Abstract: A memory cell having two mesa bipolar transistors separated by a valley in which two doped polycrystalline load resistors are formed. Doped polycrystalline conductors connect the resistors to a respective backside metallic collector contact which is between a support structure and a transistor and to a respective base.The cell is fabricated by removing a substrate upon which was formed an epitaxial layer and top support, applying a backside metallic layer, forming a bottom support, removing the top support, etching the epitaxial layer to form mesas, etching the backside metal to form discrete contacts, and forming multi-level resistors and conductors in the valley between the mesa transistors separated by insulative material.

Abstract: Low resistance contact paths to selected buried layers in dielectrically isolated islands are formed by V-etching the selected island moats in a substrate, non-selectively diffusing impurities into the surface of the substrate and selected moats, V-etching to form all the moat structure, forming a dielectric layer on said surface and moats, applying support material to over-fill said moats and cover said surface, removing the opposite surface of said substrate to expose support material, and forming devices in said opposite surface.

Abstract: Integrated circuits in dice on a wafer are qualified by providing two sets of conductors connected to each die by fusible elements, biasing the dice using said conductors during exposure to a qualifying environment, testing the fusible elements, removing the conductors and testing the circuits. Where the environment is gamma radiation, the fusible elements are tested before annealing of radiation damage and the circuits are tested before and after annealing.

Abstract: Integrated circuits in dice on a wafer are biased burn-in qualified by providing two sets of conductors connected to each die by fusible elements, biasing the dice using said conductors during the high temperature burn-in, testing the fusible elements, removing the conductors, and testing the circuits.