Abstract: Method and system aspects for enhancing a peripheral component interconnect (PCI) bus to achieve higher frequencies of operation are described. A system aspect includes at least one source synchronous strobe line for providing a source synchronous strobe signal, and at least one PCI compliant device for driving the source synchronous strobe signal to clock data and address on and off a PCI bus, wherein a cycle time for data transactions is reduced. With the present invention, significantly higher frequency capability of PCI is enabled by defining a different clocking signal and protocol for clocking data on and off the bus. A very significant timing budget savings results through the use of a source synchronous strobe for clocking data. Cycle time for bus transactions is therefore reduced, so that the frequency of operation for a synchronous bus is increased.