Abstract: A nanosecond pulser system is disclosed. In some embodiments, the nanosecond pulser system may include a nanosecond pulser having a nanosecond pulser input; a plurality of switches coupled with the nanosecond pulser input; one or more transformers coupled with the plurality of switches; and an output coupled with the one or more transformers and providing a high voltage waveform with a amplitude greater than 2 kV and a frequency greater than 1 kHz based on the nanosecond pulser input. The nanosecond pulser system may also include a control module coupled with the nanosecond pulser input; and an control system coupled with the nanosecond pulser at a point between the transformer and the output, the control system providing waveform data regarding an high voltage waveform produced at the point between the transformer and the output.

Abstract: In an embodiment, a system includes a resource. The system also includes a first processor having a load/store functional unit. The load/store functional unit is to attempt to access the resource based on access requests. The first processor includes a congestion detection logic to detect congestion of access of the resource based on a consecutive number of negative acknowledgements received in response to the access requests prior to receipt of a positive acknowledgment in response to one of the access requests within a first time period.

Abstract: In an embodiment, a system includes a resource. The system also includes a first processor having a load/store functional unit. The load/store functional unit is to attempt to access the resource based on access requests. The first processor includes a congestion detection logic to detect congestion of access of the resource based on a consecutive number of negative acknowledgements received in response to the access requests prior to receipt of a positive acknowledgment in response to one of the access requests within a first time period.

Abstract: A processor core includes multiple execution units, such as a first execution unit and a second execution unit. The first execution unit may include a first functional component that supports a superscalar pipeline. The second execution unit may include a second functional component supporting a scalar pipeline. The processor core may operate in a high-performance mode by using the first execution unit and powering down the second execution unit and operate in a low-power mode by using the second execution unit and powering down the first execution unit. The processor core may include common elements shared between the multiple execution units, such as a common instruction cache, data cache, register file(s), and more.

Abstract: In an embodiment, a system includes a resource. The system also includes a first processor having a load/store functional unit. The load/store functional unit is to attempt to access the resource based on access requests. The first processor includes a congestion detection logic to detect congestion of access of the resource based on a consecutive number of negative acknowledgements received in response to the access requests prior to receipt of a positive acknowledgment in response to one of the access requests within a first time period.

Abstract: In an embodiment, a system includes a resource. The system also includes a first processor having a load/store functional unit. The load/store functional unit is to attempt to access the resource based on access requests. The first processor includes a congestion detection logic to detect congestion of access of the resource based on a consecutive number of negative acknowledgements received in response to the access requests prior to receipt of a positive acknowledgment in response to one of the access requests within a first time period.

Abstract: In an embodiment, a system includes a resource. The system also includes a first processor having a load/store functional unit. The load/store functional unit is to attempt to access the resource based on access requests. The first processor includes a congestion detection logic to detect congestion of access of the resource based on a consecutive number of negative acknowledgements received in response to the access requests prior to receipt of a positive acknowledgment in response to one of the access requests within a first time period.

Abstract: An address queue in a processor having the capability to track memory-dependencies of memory-access instructions is disclosed. The queue includes a first matrix of RAM cells that tracks a first dependency relationship between a plurality of instructions based upon matching virtual addresses (that identify a common cache set) and the order of instructions in the queue. To facilitate out-of-order instruction execution, dependencies may be tracked before virtual addresses are actually calculated based upon a presumption of dependency. Such dependency is dynamically corrected as addresses become available. The same comparison mechanism used to determine matching virtual addresses for the dependency relationship may also be used to read status bits of a cache set being accessed.

Abstract: The present invention is directed to a diagnostic system which utilizes a microprocessor within the power module to control the diagnostic function of all field replaceable modules powered thereby; additional diagnostic hardware being located on each replaceable module which may be utilized in normal operation for functions of the module and, on an interrupt basis, it is utilized in diagnostic functions; the diagnostic hardware in the power module serving to collect the diagnostic test data from all the functional modules powered thereby, the data being transmitted thereto over a diagnostic data bus. If a plurality of power supplies are present in the system, each power supply has a microprocessor for control, each such microprocessor being coupled to the replaceable modules and the diagnostic circuitry therein; a bus being provided between the processors in the power supplies so that one such microprocessor can become a master diagnostic to process all the diagnostic messages from the system.

Abstract: A method and apparatus for positioning nuts to be welded to a base such as a steel sheet. The base is located between a pair of relatively movable welding electrodes, one of which has a retractable nut supporting and locating pin with a tapered shoulder, the pin being movable in the electrode and extending from its contact face. A nut is placed on the pin and locked onto the tapered shoulder. As the electrodes move together to a welding position the supporting and locating pin is depressed so that the nut comes into engagement with the contact face of the respective electrode. The nut is consequently freed from its taper lock on the supporting and locating pin as it is pressed against the base by the contact face of the respective electrode. Welding current is then passed between the electrodes through the nut and the base to weld the nut in place.