Abstract: A processor for controlling a sensorless, brushless DC motor is disclosed comprising a first output for providing a control signal to a potentiometer controlling the speed and voltage of the DC motor. The processor also includes a second input for receiving a back-EMF voltage from an open phase of a three phase winding. The processor determines a digital error signal from the back-EMF voltage and generates a control signal responsive to the digital error signal. The control signal decreases the speed of the motor when the digital error signal is in a first range. The processor decreases both the speed and voltage of the motor when the digital error signal is in a second range. The processor increases the speed of the motor when the digital error signal is in a third range. The processor increases both the speed and voltage of the motor when the digital error signal is in a fourth range.