Patents by Inventor Kenneth Allen Honer
Kenneth Allen Honer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8735205Abstract: A method of fabricating a microelectronic unit can include providing a semiconductor element having front and rear surfaces, a plurality of conductive pads each having a top surface exposed at the front surface and a bottom surface remote from the top surface, and a first opening extending from the rear surface towards the front surface. The method can also include forming at least one second opening extending from the first opening towards the bottom surface of a respective one of the pads. The method can also include forming a conductive via, a conductive interconnect, and a contact, the conductive via in registration with and in contact with the conductive pad and extending within the second opening, the contact exposed at an exterior of the microelectronic unit, the conductive interconnect electrically connecting the conductive via with the contact and extending away from the via at least partly within the first opening.Type: GrantFiled: November 8, 2012Date of Patent: May 27, 2014Assignee: Invensas CorporationInventors: Belgacem Haba, Kenneth Allen Honer, David B. Tuckerman, Vage Oganesian
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Publication number: 20130316501Abstract: A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals.Type: ApplicationFiled: July 31, 2013Publication date: November 28, 2013Applicant: TESSERA, INC.Inventors: Kenneth Allen Honer, Philip Damberg
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Patent number: 8508036Abstract: A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals.Type: GrantFiled: May 11, 2007Date of Patent: August 13, 2013Assignee: Tessera, Inc.Inventors: Kenneth Allen Honer, Philip Damberg
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Patent number: 8405196Abstract: A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias.Type: GrantFiled: February 26, 2008Date of Patent: March 26, 2013Assignee: DigitalOptics Corporation Europe LimitedInventors: Belgacem Haba, Kenneth Allen Honer, David B. Tuckerman, Vage Oganesian
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Patent number: 8387531Abstract: An impact switch includes a housing having a wall including at least two electrically conductive contact elements spaced apart from one another. The switch includes an inertial body having a conductive surface disposed in a tapered aperture and electrically connecting the contact elements to one another in a switch closed condition. An impact switch for rapidly firing an explosive device is provided.Type: GrantFiled: February 27, 2008Date of Patent: March 5, 2013Assignee: Tessera, Inc.Inventors: Kenneth Allen Honer, Rolfe Tyson Gustus, Ilyas Mohammed
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Patent number: 8310036Abstract: A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias.Type: GrantFiled: May 21, 2010Date of Patent: November 13, 2012Assignee: DigitalOptics Corporation Europe LimitedInventors: Belgacem Haba, Kenneth Allen Honer, David B. Tuckerman, Vage Oganesian
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Patent number: 8269319Abstract: Various structures chip packages are disclosed including a magnetoresistive random access memory (“MRAM”) device and a magnetic shield structure. The magnetic shield structure may be made from material having either ferromagnetic or diamagnetic material and may be shaped and incorporated into the chip package to divert stray magnetic fields away from the MRAM device.Type: GrantFiled: October 10, 2007Date of Patent: September 18, 2012Assignee: Tessera, Inc.Inventors: Kenneth Allen Honer, Guilian Gao, William Walter Carlson, Michael Warner
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Patent number: 8143095Abstract: A method is provided of forming a capped chip which includes a conductive interconnect exposed through an opening in the cap. A cap having openings extending between outer and inner surfaces is aligned and joined to a chip. A mass of fusible conductive material is positioned through a first such opening onto a first such bond pad of the chip. The positioned mass is heated to bond the mass to the first bond pad. The steps of positioning and heating the mass form at least a portion of a conductive interconnect extending from the first bond pad at least partially through the first opening.Type: GrantFiled: December 28, 2005Date of Patent: March 27, 2012Assignee: Tessera, Inc.Inventor: Kenneth Allen Honer
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Patent number: 8053281Abstract: A method is provided for forming a microelectronic package at a wafer level. Such method can include providing a semiconductor wafer having a surface with a pattern of electrical contacts thereon. An interposer component can be provided which has a compliant dielectric layer bonded to a conductive layer. A pattern of holes can be formed through the compliant dielectric layer and the conductive layer which corresponds to the pattern of electrical contacts. The compliant dielectric layer can be contacted with the semiconductor wafer surface so that the pattern of holes is in an aligned position with the pattern of contacts and the compliant dielectric layer and the semiconductor wafer surface then bonded in the aligned position to unite the semiconductor wafer and the interposer component to form a wafer level semiconductor package. The wafer level semiconductor package can be diced to form individual semiconductor chip packages.Type: GrantFiled: December 4, 2008Date of Patent: November 8, 2011Assignee: Tessera, Inc.Inventors: Kenneth Allen Honer, Belgacem Haba, David Ovrutsky, Charles Rosenstein, Guilian Gao
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Patent number: 7858445Abstract: A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges bounding the lid, at least one of the edges including one or more outer portions and one or more recesses extending laterally inwardly from the outer portions, with the contacts being aligned with the recesses and exposed through them.Type: GrantFiled: September 15, 2008Date of Patent: December 28, 2010Assignee: Tessera, Inc.Inventors: Kenneth Allen Honer, Giles Humpston, David B. Tuckerman, Michael J. Nystrom
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Publication number: 20100242269Abstract: An electronic camera module incorporates a sensor unit (20) having a semiconductor chip (22) such as a CCD imager and a cover (34) overlying the front surface of the chip. An optical unit (50) includes one or more optical elements such as lenses (58). The optical unit has engagement features (64) which abut alignment features on the sensor unit as, for example, portions (44) of the cover outer surface (38), so as to maintain a precise relationship between the optical unit and sensor unit.Type: ApplicationFiled: June 10, 2010Publication date: September 30, 2010Applicant: TESSERA, INC.Inventors: Giles Humpston, Kenneth Allen Honer, David B. Tuckerman
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Publication number: 20100225006Abstract: A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias.Type: ApplicationFiled: May 21, 2010Publication date: September 9, 2010Applicant: TESSERA, INC.Inventors: Belgacem Haba, Kenneth Allen Honer, David B. Tuckerman, Vage Oganesian
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Patent number: 7763983Abstract: A method of manufacturing a microelectronic package. The method includes the steps of attaching at least one microelectronic element to a tape having upper terminals projecting upwardly from an upper surface of a dielectric layer, so that top surfaces of the terminals are disposed coplanar with or above a top surface of the microelectronic element after the attaching step, electrically connecting the microelectronic element to at least some of the upper terminals; and further includes the step of applying an encapsulant to cover at least a portion of the upper surface of the dielectric layer, leaving the upper terminals surfaces of the terminals exposed.Type: GrantFiled: July 2, 2007Date of Patent: July 27, 2010Assignee: Tessera, Inc.Inventors: Kenneth Allen Honer, Jae M. Park
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Patent number: 7566853Abstract: Image sensors are provided having a plurality of photodetectors in a detector layer Optionally, an optically transparent substrate is provided for a rear-illuminated sensor architecture. The photodetectors may be arranged in three or more arrays. Typically, each array is contiguous and is associated with light of a different color and/or wavelength. In addition, the arrays may be coplanar, or, in the alternative, located at increasing distances from a light-receiving surface in an at least partially nonoverlapping manner. Also provided are image sensor packages.Type: GrantFiled: December 23, 2005Date of Patent: July 28, 2009Assignee: Tessera, Inc.Inventors: David B. Tuckerman, Kenneth Allen Honer, Bruce M. McWilliams, Nicholas J. Colella, Charles Liam Goudge
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Publication number: 20090162975Abstract: A method is provided for forming a microelectronic package at a wafer level. Such method can include providing a semiconductor wafer having a surface with a pattern of electrical contacts thereon. An interposer component can be provided which has a compliant dielectric layer bonded to a conductive layer. A pattern of holes can be formed through the compliant dielectric layer and the conductive layer which corresponds to the pattern of electrical contacts. The compliant dielectric layer can be contacted with the semiconductor wafer surface so that the pattern of holes is in an aligned position with the pattern of contacts and the compliant dielectric layer and the semiconductor wafer surface then bonded in the aligned position to unite the semiconductor wafer and the interposer component to form a wafer level semiconductor package. The wafer level semiconductor package can be diced to form individual semiconductor chip packages.Type: ApplicationFiled: December 4, 2008Publication date: June 25, 2009Applicant: Tessera, Inc.Inventors: Kenneth Allen Honer, Belgacem Haba, David Ovrutsky, Charles Rosenstein, Guilian Gao
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Publication number: 20090023249Abstract: A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges bounding the lid, at least one of the edges including one or more outer portions and one or more recesses extending laterally inwardly from the outer portions, with the contacts being aligned with the recesses and exposed through them.Type: ApplicationFiled: September 15, 2008Publication date: January 22, 2009Applicant: Tessera, Inc.Inventors: Kenneth Allen Honer, Giles Humpston, David B. Tuckerman, Michael J. Nystrom
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Publication number: 20090008795Abstract: A method of manufacturing a microelectronic package. The method includes the steps of attaching at least one microelectronic element to a tape having upper terminals projecting upwardly from an upper surface of a dielectric layer, so that top surfaces of the terminals are disposed coplanar with or above a top surface of the microelectronic element after the attaching step, electrically connecting the microelectronic element to at least some of the upper terminals; and further includes the step of applying an encapsulant to cover at least a portion of the upper surface of the dielectric layer, leaving the upper terminals surfaces of the terminals exposed.Type: ApplicationFiled: July 2, 2007Publication date: January 8, 2009Applicant: Tessera, Inc.Inventors: Kenneth Allen Honer, Jae M. Park
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Publication number: 20080277775Abstract: A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals.Type: ApplicationFiled: May 11, 2007Publication date: November 13, 2008Applicant: Tessera, Inc.Inventors: Kenneth Allen Honer, Philip Damberg
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Patent number: 7449779Abstract: A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges bounding the lid, at least one of the edges including one or more outer portions and one or more recesses extending laterally inwardly from the outer portions, with the contacts being aligned with the recesses and exposed through them.Type: GrantFiled: December 30, 2005Date of Patent: November 11, 2008Assignee: Tessera, Inc.Inventors: Kenneth Allen Honer, Giles Humpston, David B. Tuckerman, Michael J. Nystrom
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Publication number: 20080246136Abstract: A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias.Type: ApplicationFiled: February 26, 2008Publication date: October 9, 2008Applicant: Tessera, Inc.Inventors: Belgacem Haba, Kenneth Allen Honer, David B. Tuckerman, Vage Oganesian