Abstract: A multi-phase switching mode power supply (SMPS) with adaptive synchronous drivers is provided. A pulse width modulator creates n periodic interleaved modulation pulses having a pulse width responsive to a load voltage. Modulation pulses are converted into selectively enabled driver pulses having a duty cycle responsive to the modulation pulse. The polarity of the voltage is detected at a completion of each driver pulse duty cycle. A comparator signal is supplied in response to comparing detected voltages to a reference voltage, and in turn, driver gating signals are supplied to selectively enable driver pulses in response to analyzing comparator signals. The comparator signals are summed and integrated. Driver pulses are enabled or disabled in response to the integrated sum. Energy is stored from each driver pulse into a corresponding inductor, and supplied as current to a load, creating the load voltage.

Abstract: A multi-phase switching mode power supply (SMPS) with adaptive synchronous drivers is provided. A pulse width modulator creates n periodic interleaved modulation pulses having a pulse width responsive to a load voltage. Modulation pulses are converted into selectively enabled driver pulses having a duty cycle responsive to the modulation pulse. The polarity of the voltage is detected at a completion of each driver pulse duty cycle. A comparator signal is supplied in response to comparing detected voltages to a reference voltage, and in turn, driver gating signals are supplied to selectively enable driver pulses in response to analyzing comparator signals. The comparator signals are summed and integrated. Driver pulses are enabled or disabled in response to the integrated sum. Energy is stored from each driver pulse into a corresponding inductor, and supplied as current to a load, creating the load voltage.

Abstract: Systems and methods for generating clock phase signals with accurate timing relations are disclosed. For example, four clock signals spaced by 90 degrees can be generating from differential CML clock signals. A CML to CMOS converter converts the differential CML clock signals to differential CMOS clock signals and provides duty cycle correction. Delay cells produce delayed clock signals from the differential CMOS clock signals. The differential CMOS clock signals and the delayed clock signals are logically combined to produce four quarter clock signals having active times of one-quarter clock period. Set-reset latches produce the four clock signals from the quarter clock signals. A calibration module control delays of the delay cells and controls the duty cycle correction of the CML to CMOS converter to adjust the timing relationships of the four clock signals. The four clock signals may be used, for example, in a deserializer.

Abstract: Systems and methods for generating clock phase signals with accurate timing relations are disclosed. For example, four clock signals spaced by 90 degrees can be generating from differential CML clock signals. A CML to CMOS converter converts the differential CML clock signals to differential CMOS clock signals and provides duty cycle correction. Delay cells produce delayed clock signals from the differential CMOS clock signals. The differential CMOS clock signals and the delayed clock signals are logically combined to produce four quarter clock signals having active times of one-quarter clock period. Set-reset latches produce the four clock signals from the quarter clock signals. A calibration module control delays of the delay cells and controls the duty cycle correction of the CML to CMOS converter to adjust the timing relationships of the four clock signals. The four clock signals may be used, for example, in a deserializer.

Abstract: A Class-D switching amplifier (30, 40) having a ternary mode of operation. Signal processing (21, 22) is provided to eliminate the potential of crosstalk within one channel by introducing a time delay into the system. A susceptible crosstalk point is moved away from a zero-crossing point to a higher power level, which is advantageous in low-end audio applications. A time delay is introduced to one ramp signal (RAMPB) in the first implementation (30), and an in-sync generator (42) is utilized in another implementation (40) using offset switching in the comparitors (40, 42) to create the time delay (&Dgr;t).