Abstract: A novel method for scanning bit parity in a memory array, and a circuit for implementing it, are disclosed. In a memory array that has one or more rows of memory cells, the method for checking data parity includes storing a plurality of data bits in the memory cells, scanning a row of memory cells independently of a memory read operation to ascertain the stored data bits; and determining parity for the row of memory cells by the results of the scanning. The method is accomplished by means of a dedicated parity scanning circuit.

Abstract: CAM-based search engines may be configured to support multiple databases within a CAM core. These databases may represent tables for different applications, which can be searched sequentially in response to a single indirect instruction that is loaded during a control cycle. The databases to be searched may be identified by a multi-database search instruction that is loaded during a single data cycle, which may overlap with the control cycle. In some cases, the databases may be searched using variations of a primary search key, so that it is unnecessary to repeatedly load the entire search key across a network interface for each search operation within a respective database. Instead, shorter replacement key segments may be loaded for each of a plurality of the search operations and these replacement key segments may be combined with one or more segments of the primary search key in the CAM core to define a desired search key for a respective search operation.

Abstract: CAM-based search engines may be configured to support multiple databases within a CAM core. These databases may represent tables for different applications, which can be searched sequentially in response to a single indirect instruction that is loaded during a control cycle. The databases to be searched may be identified by a multi-database search instruction that is loaded during a single data cycle, which may overlap with the control cycle. In some cases, the databases may be searched using variations of a primary search key, so that it is unnecessary to repeatedly load the entire search key across a network interface for each search operation within a respective database. Instead, shorter replacement key segments may be loaded for each of a plurality of the search operations and these replacement key segments may be combined with one or more segments of the primary search key in the CAM core to define a desired search key for a respective search operation.

Abstract: An ATM switch according to the present invention includes a memory and a control circuit. The ATM switch generates a connection table in a memory, generates a multicast master entry including a limit field and a count field. The multicast master entry also includes address locations at which multicast ATM cells are stored. The ATM switch further generates one or more multicast member entries associated with said multicast master entry in said connection table, each multicast member entry identifying a destination connection on which said multicast ATM cells are to be transmitted. Further, the count field is initialized and the limit field is set at a predetermined value. The master entry is then determined to be active or inactive depending on a comparison between the count field and the limit field.

Abstract: Content addressable memory (CAM) devices include CAM logic that is configured to pass an instruction received at an instruction input port to an instruction output port without inspection or alteration. This enables the CAM devices to be operated as equivalent devices within a cascaded chain of CAM devices that collectively form multiple databases within a lookup engine having distributed CAM control. This CAM logic may include an input instruction register that is configured to latch the instruction received at the instruction input port and an output instruction register that is configured to latch the instruction received from the input instruction register. This CAM logic may also include an instruction FIFO that is configured to buffer instructions received from the input instruction register.

Abstract: Search engine devices include a content addressable memory (CAM) core having a plurality of CAM array blocks therein and a control circuit that is electrically coupled to the CAM core. The control circuit is configured to support internal error detection and correction operations using modified Hamming code words. These operations are performed without significant impact on the compare bandwidth of the search engine device, even when operations to read entries from the CAM core are performed as foreground operations that may block concurrent search operations. The control circuit may perform the error detection and correction operations by issuing multiple read instructions. These instructions include a first instruction (e.g., error check instruction) to read at least a first entry into the CAM core for the purpose of error detection and then, in response to detecting the first entry as erroneous, issuing a second instruction to read the first entry from the CAM core.

Abstract: An ATM switch for transmitting a multicast ATM cell includes a memory, a control circuit, and a cell memory. The control circuit maintains in the memory a connection table which includes a multicast master entry and one or more multicast member entries associated with the multicast master entry. The cell memory stores one or more ATM cells, including the multicast ATM cell. The multicast master entry holds an address of the cell memory at which the multicast ATM cell is stored. The multicast member entries are linked to each other through a circular double linked list.