Patents by Inventor Kenneth Brennan

Kenneth Brennan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060160299
    Abstract: The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).
    Type: Application
    Filed: January 18, 2005
    Publication date: July 20, 2006
    Inventors: Satyavolu Rao, Darius Crenshaw, Stephan Grunow, Kenneth Brennan, Somit Joshi, Montray Leavy, Phillip Matz, Sameer Ajmera, Yuri Solomentsev
  • Publication number: 20060134809
    Abstract: An integrated circuit capacitor having a bottom plate 50a, a dielectric layer 250?, and a ferromagnetic top plate 20a. Also, a method of manufacturing an integrated circuit on a semiconductor wafer. The method comprising forming a bottom plate of a capacitor 50a and a bottom portion of an induction coil 50a, forming an etch stop layer 250?, forming a ferromagnetic capacitor top plate 20a and a ferromagnetic core 20b, forming a top portion of the induction coil 50b plus vias 50c that couple the top portion of the induction coil 50b to the bottom portion of the induction coil 50c.
    Type: Application
    Filed: January 26, 2006
    Publication date: June 22, 2006
    Inventors: Kenneth Brennan, Satyavolu Papa Rao
  • Publication number: 20060128036
    Abstract: An integrated circuit capacitor having a bottom plate 50a, a dielectric layer 250?, and a ferromagnetic top plate 20a. Also, a method of manufacturing an integrated circuit on a semiconductor wafer. The method comprising forming a bottom plate of a capacitor 50a and a bottom portion of an induction coil 50a, forming an etch stop layer 250?, forming a ferromagnetic capacitor top plate 20a and a ferromagnetic core 20b, forming a top portion of the induction coil 50b plus vias 50c that couple the top portion of the induction coil 50b to the bottom portion of the induction coil 50c.
    Type: Application
    Filed: December 10, 2004
    Publication date: June 15, 2006
    Inventors: Kenneth Brennan, Satyavolu Papa Rao
  • Publication number: 20060022787
    Abstract: An inductor structure (102) formed in an integrated circuit (100) is disclosed, and includes a first isolation layer (106) and a first core plate (104) disposed over or within the first isolation layer (106, 114). The first core plate (104) includes a plurality of electrically coupled conductive traces composed of a conductive ferromagnetic material layer. A second isolation layer (108) overlies the first isolation layer and an inductor coil (102) composed of a conductive material layer (118) is formed within the second isolation layer (108). Another core plate may be formed over the coil. The one or more core plates increase an inductance (L) of the inductor coil (102).
    Type: Application
    Filed: July 30, 2004
    Publication date: February 2, 2006
    Inventors: Kenneth Brennan, Satyavolu Papa Rao, Byron Williams
  • Publication number: 20060024899
    Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.
    Type: Application
    Filed: July 31, 2004
    Publication date: February 2, 2006
    Inventors: Darius Crenshaw, Byron Williams, Alwin Tsao, Hisashi Shichijo, Satyavolu Papa Rao, Kenneth Brennan, Steven Lytle