Abstract: A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

Abstract: A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

Abstract: A method for forming an interconnect wiring structure, such as a fuse structure, comprises forming an opening in an insulating layer using a phase shift mask (the opening having vertical sidewalls sloped sidewalls and horizontal surfaces), depositing a conductive material in the opening and removing the conductive material from the sloped sidewalls and horizontal surfaces, wherein the conductive material remains on the vertical sidewalls as fuse links.

Abstract: A structure and method for making a cavity fuse over a gate conductor stack.

Abstract: A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

Abstract: A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

Abstract: A method for forming an interconnect wiring structure, such as a fuse structure, comprises forming an opening in an insulating layer using a phase shift mask (the opening having vertical sidewalls sloped sidewalls and horizontal surfaces), depositing a conductive material in the opening and removing the conductive material from the sloped sidewalls and horizontal surfaces, wherein the conductive material remains on the vertical sidewalls as fuse links.

Abstract: A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

Abstract: The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks.

Abstract: A process for selective electroless plating onto a substrate, including providing a substrate having at least a catalytic surface; providing a plating gel comprising a carrier vehicle, an electroless platable metal compound capable of providing metal ions to the carrier vehicle at a specific pH, a reducing agent, and a polymeric thickening agent; applying said plating gel to the substrate surface in a selected pattern, and inducing plating of said metal on the substrate surface in said selected pattern. A stabilizer, and/or buffering and/or organic chelating agent, and/or surfactant and/or a humectant may be included in the plating gel. Preferably the metal compound is a gold complex, and the substrate is aluminum nitride.

Abstract: A method for forming an interconnect wiring structure, such as a fuse structure, comprises forming an opening in an insulating layer using a phase shift mask (the opening having vertical sidewalls sloped sidewalls and horizontal surfaces), depositing a conductive material in the opening and removing the conductive material from the sloped sidewalls and horizontal surfaces, wherein the conductive material remains on the vertical sidewalls as fuse links.

Abstract: A semiconductor structure comprising a semiconductor substrate, an electrically conductive level on the substrate and a metal fuse located at the conductive level wherein the fuse comprises a self-aligned dielectric etch stop layer thereon is provided along with processes for its fabrication.

Abstract: A programmable/reprogrammable fuse arrangement that includes two fuse links provided each with an output port and an exclusive-or gate connected to the output port of each of the two fuses, wherein the fuse arrangement is reprogrammed by successively blowing both of the two fuse links is described. The programmable/reprogrammable fuse arrangement can be extended to a plurality of fuses and cascaded exclusive-ORs such that each fuse link provides one leg of the gate and the previous stage, the second. Thus, for N fuse links and N exclusive-ORs, the fuse arrangement thus formed can be reprogrammed a total of N times by sequentially blowing one fuse link at a time. The arrangement ceases to be reprogrammable once all the fuse links have been blown. The reprogrammable fuse arrangement is of particular importance for semiconductor memories and microprocessors, as for instance, for bringing in-line redundancy units attached to a fuse link.

Abstract: The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks.

Abstract: A waste fuel incineration process and system operates at very high temperatures with excess under fire air for high efficiency combustion of waste as a fuel and for decomposition of any toxic waste. The system is applicable for clean burning volume reduction of waste and for power generation and co-generation of heat. The control elements are constructed and arranged and the control circuit programmed for maintaining the primary combustion temperature at a target temperature selected in the range of approximately 1600.degree.-1800.degree. F. (871.degree.-982.degree. C.