Patents by Inventor Kenneth C. Dyer
Kenneth C. Dyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230253974Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.Type: ApplicationFiled: January 3, 2023Publication date: August 10, 2023Inventors: Masum HOSSAIN, Kenneth C. DYER, Nhat NGUYEN, Shankar TANGIRALA
-
Patent number: 11671108Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.Type: GrantFiled: April 25, 2022Date of Patent: June 6, 2023Assignee: Rambus Inc.Inventors: Kenneth C. Dyer, Marcus Van Ierssel
-
Patent number: 11575386Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.Type: GrantFiled: May 10, 2021Date of Patent: February 7, 2023Assignee: Rambus Inc.Inventors: Masum Hossain, Kenneth C. Dyer, Nhat Nguyen, Shankar Tangirala
-
Publication number: 20220321138Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.Type: ApplicationFiled: April 25, 2022Publication date: October 6, 2022Inventors: Kenneth C. DYER, Marcus VAN IERSSEL
-
Patent number: 11342929Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.Type: GrantFiled: July 30, 2019Date of Patent: May 24, 2022Assignee: Rambus Inc.Inventors: Kenneth C. Dyer, Marcus Van Ierssel
-
Publication number: 20210336627Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.Type: ApplicationFiled: May 10, 2021Publication date: October 28, 2021Inventors: Masum HOSSAIN, Kenneth C. DYER, Nhat NGUYEN, Shankar TANGIRALA
-
Patent number: 11038514Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.Type: GrantFiled: May 28, 2020Date of Patent: June 15, 2021Assignee: Rambus Inc.Inventors: Masum Hossain, Kenneth C. Dyer, Nhat Nguyen, Shankar Tangirala
-
Publication number: 20210167789Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.Type: ApplicationFiled: July 30, 2019Publication date: June 3, 2021Inventors: Kenneth C. DYER, Marcus VAN IERSSEL
-
Publication number: 20200366304Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.Type: ApplicationFiled: May 28, 2020Publication date: November 19, 2020Inventors: Masum HOSSAIN, Kenneth C. DYER, Nhat NGUYEN, Shankar TANGIRALA
-
Patent number: 10707885Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.Type: GrantFiled: February 11, 2019Date of Patent: July 7, 2020Assignee: Rambus Inc.Inventors: Masum Hossain, Kenneth C. Dyer, Nhat Nguyen, Shankar Tangirala
-
Patent number: 10523229Abstract: An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M?1 sampling phases of the M sampling phases. The phase control circuit comprises M?1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M?1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.Type: GrantFiled: December 20, 2018Date of Patent: December 31, 2019Assignee: Rambus Inc.Inventor: Kenneth C. Dyer
-
Publication number: 20190245548Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.Type: ApplicationFiled: February 11, 2019Publication date: August 8, 2019Inventors: Masum Hossain, Kenneth C. Dyer, Nhat Nguyen, Shankar Tangirala
-
Publication number: 20190238149Abstract: An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M?1 sampling phases of the M sampling phases. The phase control circuit comprises M?1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M?1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.Type: ApplicationFiled: December 20, 2018Publication date: August 1, 2019Inventor: Kenneth C. Dyer
-
Patent number: 10230384Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.Type: GrantFiled: November 20, 2017Date of Patent: March 12, 2019Assignee: Rambus Inc.Inventors: Masum Hossain, Kenneth C. Dyer, Nhat Nguyen, Shankar Tangirala
-
Patent number: 10177778Abstract: An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M?1 sampling phases of the M sampling phases. The phase control circuit comprises M?1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M?1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.Type: GrantFiled: November 27, 2017Date of Patent: January 8, 2019Assignee: Rambus Inc.Inventor: Kenneth C. Dyer
-
Publication number: 20180167080Abstract: An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M?1 sampling phases of the M sampling phases. The phase control circuit comprises M?1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M?1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.Type: ApplicationFiled: November 27, 2017Publication date: June 14, 2018Inventor: Kenneth C. Dyer
-
Publication number: 20180167076Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.Type: ApplicationFiled: November 20, 2017Publication date: June 14, 2018Inventors: Masum Hossain, Kenneth C. Dyer, Nhat Nguyen, Shankar Tangirala
-
Publication number: 20150207718Abstract: A method of identifying and correcting each of the changes that may occur with wire pairs between the transmitter and receiver in Ethernet 10GBase-T cabling is provided. The method includes four wire pairs A, B, C and D, a polarity swapping and scrambler state machine that determine if the chosen pair matches the requirements for pair A. A slave Tap state machine generates a rule for correct B, C and D patterns based on a pair chosen as pair A. The cables B, C and D are iteratively swapped to rearrange the pair mapping into the polarity swap state machine, and a deskew state machine identifies the latency difference between the different pairs. If the rules are not satisfied, a new pair A is designated at the swapping state machine and the process is repeated until the rules are satisfied.Type: ApplicationFiled: February 23, 2015Publication date: July 23, 2015Inventors: KENNETH C. DYER, PRAVEEN GOPALAPURAM, MANI KUMARAN, TAMLEIGH ROSS
-
Patent number: 8994926Abstract: An optical sensor includes a driver, light detector and echo canceller. The driver is adapted to selectively drive a light source. The light detector is adapted to produce a detection signal indicative of an intensity of light detected by the light detector. The echo canceller is adapted to produce an echo cancellation signal that is combined with the detection signal produced by the light detector to produce an echo cancelled detection signal having a predetermined target magnitude (e.g., zero). The echo canceller includes a coefficient generator that is adapted to produce echo cancellation coefficients indicative of distance(s) to one or more objects, if any, within the sense region of the optical sensor. The optical sensor can also include a proximity detector adapted to detect distance(s) to one or more objects within the sense region of the optical sensor based on the echo cancellation coefficients generated by the coefficient generator.Type: GrantFiled: June 7, 2012Date of Patent: March 31, 2015Assignee: Intersil Americas LLCInventor: Kenneth C. Dyer
-
Patent number: 8964578Abstract: A line driver circuit an method for protecting the line driver circuit from overdrive that includes generating an output signal for a transformer coupled to a load, and comparing a voltage of the output signal to a threshold voltage value. If the comparison indicates overload, the method further includes generating a control signal to reduce an amplitude of the output signal.Type: GrantFiled: April 14, 2011Date of Patent: February 24, 2015Assignee: Vintomie Networks B.V., LLCInventor: Kenneth C. Dyer