Patents by Inventor Kenneth C. Haren
Kenneth C. Haren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230185747Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller’s performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: ApplicationFiled: February 8, 2023Publication date: June 15, 2023Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Patent number: 11604746Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: GrantFiled: July 22, 2020Date of Patent: March 14, 2023Assignee: SK hynix NAND Product Solutions Corp.Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Patent number: 11449446Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: GrantFiled: July 22, 2020Date of Patent: September 20, 2022Assignee: Intel CorporationInventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Publication number: 20200349100Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: ApplicationFiled: July 22, 2020Publication date: November 5, 2020Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Patent number: 9935653Abstract: Methods and apparatus related to enhanced Cyclical Redundancy Check (CRC) circuit based on Galois-Field arithmetic are described. In one embodiment, a plurality of exclusive OR logic include first exclusive OR logic and second exclusive OR logic. First Galois Field multiplier logic multiplies a first output from the first exclusive OR logic and a first portion of a plurality of portions of the input data. Second Galois Field multiplier logic multiplies a second output from the second exclusive OR logic and a second portion of the plurality of portions of the input data. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 28, 2015Date of Patent: April 3, 2018Assignee: Intel CorporationInventors: Sivakumar Radhakrishnan, Sin S. Tan, Kenneth C. Haren, Mark A. Schmisseur
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Publication number: 20170187389Abstract: Methods and apparatus related to enhanced Cyclical Redundancy Check (CRC) circuit based on Galois-Field arithmetic are described. In one embodiment, a plurality of exclusive OR logic include first exclusive OR logic and second exclusive OR logic. First Galois Field multiplier logic multiplies a first output from the first exclusive OR logic and a first portion of a plurality of portions of the input data. Second Galois Field multiplier logic multiplies a second output from the second exclusive OR logic and a second portion of the plurality of portions of the input data. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 28, 2015Publication date: June 29, 2017Applicant: Intel CorporationInventors: Sivakumar Radhakrishnan, Sin S. Tan, Kenneth C. Haren, Mark A. Schmisseur
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Publication number: 20160335208Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: ApplicationFiled: July 29, 2016Publication date: November 17, 2016Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Patent number: 9417821Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: GrantFiled: September 30, 2011Date of Patent: August 16, 2016Assignee: Intel CorporationInventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Patent number: 9141469Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.Type: GrantFiled: November 18, 2013Date of Patent: September 22, 2015Assignee: Intel CorporationInventors: Sivakumar Radhakrishnan, Mark A. Schmisseur, Sin S. Tan, Kenneth C. Haren, Thomas C. Brown, Pankaj Kumar, Vinodh Gopal, Wajdi K. Feghali
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Publication number: 20140189212Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: ApplicationFiled: September 30, 2011Publication date: July 3, 2014Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Publication number: 20140082451Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.Type: ApplicationFiled: November 18, 2013Publication date: March 20, 2014Inventors: Sivakumar Radhakrishnan, Mark A. Schmisseur, Sin S. Tan, Kenneth C. Haren, Thomas C. Brown, Pankaj Kumar, Vinodh Gopal, Wajdi K. Feghali
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Patent number: 8607129Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.Type: GrantFiled: July 1, 2011Date of Patent: December 10, 2013Assignee: Intel CorporationInventors: Sivakumar Radhakrishnan, Mark A. Schmisseur, Sin S. Tan, Kenneth C. Haren, Thomas C. Brown, Pankaj Kumar, Vinodh Gopal, Wajdi K. Feghali
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Publication number: 20130007573Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.Type: ApplicationFiled: July 1, 2011Publication date: January 3, 2013Inventors: Sivakumar Radhakrishnan, Mark A. Schmisseur, Sin S. Tan, Kenneth C. Haren, Thomas C. Brown, Pankaj Kumar, Vinodh Gopal, Wajdi K. Feghali
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Patent number: 6192442Abstract: An interrupt controller includes conductors for receiving interrupt request signals, a memory, a register and control logic. Each of the interrupt request signals are capable of indicating an interrupt request. The memory is capable of storing information about the interrupt request signals, and the register is writable to identify a set of locations of the memory for scanning. The control logic scans the set of locations for interrupt requests and does not scan other locations of the memory for interrupt requests. In some cases, the number of interrupt request signals are exceeds the number of locations. For these cases, information about selected interrupt signals are stored in the locations.Type: GrantFiled: April 29, 1998Date of Patent: February 20, 2001Assignee: Intel CorporationInventors: Kenneth C. Haren, Tuan Quach