Abstract: A bit-serial multiplier has a multi-stage input data register and a multi-tiered tree of multiplexer/adder circuits coupled thereto which produces, at the output of the adder at the top tier of the tree, successive bit serial digital output codes representative of the products of a prescribed digital data code and successive input data codes as the input data codes are sequentially shifted into and through the input data register. By multiplexing the inputs to the adders of the tree to execute either an add function or to bypass data to the output successive output products codes can be generated at a twice the rate required to shift respective input codes into and through the input data register, thereby increasing the effective computational speed of the multiplier.