Abstract: Novel semiconductor devices are taught. The novel devices include a thin film transistor (TFT) with an n-type semiconductor layer to form a channel between a source and a drain. The TFT further includes a source-channel interfacial member adjacent to at least the source contact of the device to provide depletion layer control of the operation of the TFT.

Abstract: A memory-centric neural network system and operating method thereof includes: a processing unit; semiconductor memory devices coupled to the processing unit, the semiconductor memory devices containing instructions executed by the processing unit; a weight matrix constructed with rows and columns of memory cells, inputs of the memory cells of a same row being connected to one of axons, outputs of the memory cells of a same column being connected to one of neurons; timestamp registers registering timestamps of the axons and the neurons; and a lookup table containing adjusting values indexed in accordance with the timestamps, wherein the processing unit updates the weight matrix in accordance with the adjusting values.

Abstract: A memory-centric neural network system and operating method thereof includes: a processing unit; semiconductor memory devices coupled to the processing unit, the semiconductor memory devices containing instructions executed by the processing unit; a weight matrix constructed with rows and columns of memory cells, inputs of the memory cells of a same row being connected to one of axons, outputs of the memory cells of a same column being connected to one of neurons; timestamp registers registering timestamps of the axons and the neurons; and a lookup table containing adjusting values indexed in accordance with the timestamps, wherein the processing unit updates the weight matrix in accordance with the adjusting values.

Abstract: A memory-centric neural network system and operating method thereof includes: a processing unit; semiconductor memory devices coupled to the processing unit, the semiconductor memory devices contain instructions executed by the processing unit; weight matrixes including a positive weight matrix and a negative weight matrix constructed with rows and columns of memory cells, inputs of the memory cells of a same row are connected to one of Axons, outputs of the memory cells of a same column are connected to one of Neurons; timestamp registers registering timestamps of the Axons and the Neurons; and a lookup table containing adjusting values indexed in accordance with the timestamps, the processing unit updates the weight matrixes in accordance with the adjusting values.

Abstract: A memory-centric neural network system and operating method thereof includes: a processing unit; semiconductor memory devices coupled to the processing unit, the semiconductor memory devices contain instructions executed by the processing unit; a weight matrix constructed with rows and columns of memory cells, inputs of the memory cells of a same row are connected to one of Axons, outputs of the memory cells of a same column are connected to one of Neurons; timestamp registers registering timestamps of the Axons and the Neurons; and a lookup table containing adjusting values indexed in accordance with the timestamps, the processing unit updates the weight matrix in accordance with the adjusting values.

Abstract: Memory systems may include a memory storage including a fast memory portion and a slow memory portion, a software page remapping kernel driver (SPRKD) suitable for intercepting a memory management command generated by an operating system, at least one of compressing data to be written from the fast memory portion to the slow memory portion prior to execution of the operating system memory management command, and decompressing data to be written from the slow memory portion to the fast memory portion prior to execution of the operating system memory management command, and transferring either the compressed data to be written to the slow memory portion or the decompressed data to be written to the fast memory portion, and a controller suitable for executing the memory management command after the transferring by the SPRKD such that the compressing or decompressing of data is performed transparent to the operating system.

Abstract: Memory systems may include a memory storage including a dynamic random access memory (DRAM) portion, a non-volatile memory (NVM) portion, and a virtual memory (VM), a software page remapping kernel driver (SPRKD) suitable for intercepting a memory management command, the memory management command including an access to a virtual address location of the VM, and remapping the virtual address location from a physical address of the NVM portion mapped to the virtual address location to a physical address of the DRAM portion, and a controller suitable for executing the memory management command by accessing the physical address of the DRAM portion to which the virtual address location is remapped.

Abstract: A secondary bus controller allows for hot insertion and ejection of devices from the secondary bus without ceasing operations or halting software in the host computer. When a device is to be inserted a signal is sent to the secondary bus controller. The secondary bus controller suspends operation of the secondary bus, placing devices on the secondary bus in stasis. An interrupt handler reconfigures the system for the newly inserted card once it has been inserted. Attempts to access devices on the secondary bus during the insertion process may be met with a retry signal until insertion is complete. The ejection process follows similar steps, isolating and suspending operations on the secondary bus and triggering an interrupt routine in the host processor to reconfigure the system. The host processor and primary busses, along with the secondary bus controller remain active throughout the insertion or ejection processes.

Abstract: Hot-insertion/removal, herein used interchangeably with hot-docking/undocking, would enable the connection or disconnection of a fully powered bus to an expansion device with no damage or data loss to either device. Previous docking solutions typically require the docking bus to be placed into a power-off or power-managed state, which means the user would have to consciously place the system into a power-off or power-managed state before an insertion or removal could occur. The hot-docking/undocking invention is completely transparent to the end user, so it would provide tremendous flexibility and seamless insertions and removals. Hot-docking/undocking is composed of three elements: a detection of a docking/undocking situation; a placement of the docking bus into a static state; and a system reconfiguration. The present invention places the docking bus into an static state through the use of a special handshaking protocol and clock and reset signals on the expansion device.