Abstract: A dual-phase clock divider circuit provides the ability to generate high speed complementary clocks with low skew. The dual-phase clock divider circuit runs off a single clock input, such as provided by a high speed VCO. This eliminates the effect of clock skew in the highest speed portion of the circuit. The dual-phase clock divider then generates complementary outputs of low skew to be used by other clocked elements.

Abstract: A multi-clock controller circuit includes first and second inputs to which two different types of clocks, such as a crystal oscillator clock and a TTL clock, can be applied. The circuit automatically senses which of the two input clock signals is active and provides that clock signal to an output of the circuit. Power up and power down conditions are achieved without generating non-standard clock pulses on the output through use of a synchronizer stage comprising a plurality of flip flops which determines the number of input clock cycles which are received by the circuit before output clock signals for power up or power down conditions commence.

Abstract: A circuit design extending the range and linearizing the transfer characteristic of a fast voltage controlled oscillator (VCO). In addition, a multi-range VCO is described. Range extension is achieved by modifying the delay cell of a current controlled ring oscillator. The VCO transfer characteristic is linearized by piece-wise linear current control added to the delay cell. Additionally, a VCO capable of multi-range operation is provided. With the addition of multiple current sources which control booster inverter current, and by selectively enabling the additional current sources, a VCO with multiple frequency ranges can be achieved.

Abstract: A method for retransmitting selected data elements read from a memory. A first sequence of individually addressable data elements d.sub.1, d.sub.2, . . . , d.sub.n are read from the memory. First and second signals indicate whether each data element was read without or with, respectively, a transmission error. A second sequence of data elements d.sub.i, d.sub.i+1, . . . , d.sub.n, where d.sub.i is the first data element of the first sequence to have a transmission error is then retransmitted.

Abstract: A circuit for generating clock and control signals from first and second asynchronous binary signals. The circuit generates first and second pulse signals responsive to the first and second asynchronous binary signals, a clock pulse signal responsive to the first or second pulse signal, and an identification control signal to indicate which of the two binary signals is responsible for the clock signal. The circuit is also responsive to the first and second pulse signals for generating an overlap control signal to indicate overlap in the first and second pulse signals.