Abstract: A method of forming a stacked capacitor structure in a semiconductor device, having metal electrode plates. After depositing the bottom electrode layer (26) and the dielectric layer (28) of the capacitor, a rough patterning step is carried out to roughly pattern or shape the bottom electrode layer and the dielectric layer, and to expose the underlying interlayer dielectric (18). A top electrode layer (32) is then blanket deposited, and another, more precise etching step is carried out to form the final shape of the capacitor element, while leaving behind a portion of the top electrode layer on the interlayer dielectric, which forms a metal interconnect (36). In one embodiment, the electrode layers are comprised of materials having a conductivity greater than doped silicon (either poly or monocrystalline), such as a metal.