Abstract: Embodiments of the present disclosure includes systems and methods for diagnosing and correcting deficiencies in operation of integrated circuits. A set of operational data of an integrated circuit is received by a network via a communication interface. A deficiency in operation of the integrated circuit is diagnosed based on the set of operational data. A correction is generated for improving operation of the integrated circuit based on the deficiency diagnosed. The correction is transmitted over the network via the communication interface to the integrated circuit.

Abstract: Embodiments of the present disclosure includes systems and methods for diagnosing and correcting deficiencies in operation of integrated circuits. A set of operational data of an integrated circuit is received by a network via a communication interface. A deficiency in operation of the integrated circuit is diagnosed based on the set of operational data. A correction is generated for improving operation of the integrated circuit based on the deficiency diagnosed. The correction is transmitted over the network via the communication interface to the integrated circuit.

Abstract: Embodiments of the present disclosure includes systems and methods for diagnosing and correcting deficiencies in operation of integrated circuits. A set of operational data of an integrated circuit is received by a network via a communication interface. A deficiency in operation of the integrated circuit is diagnosed based on the set of operational data. A correction is generated for improving operation of the integrated circuit based on the deficiency diagnosed. The correction is transmitted over the network via the communication interface to the integrated circuit.

Abstract: Embodiments of the present disclosure includes systems and methods for diagnosing and correcting deficiencies in operation of integrated circuits. A set of operational data of an integrated circuit is received by a network via a communication interface. A deficiency in operation of the integrated circuit is diagnosed based on the set of operational data. A correction is generated for improving operation of the integrated circuit based on the deficiency diagnosed. The correction is transmitted over the network via the communication interface to the integrated circuit.

Abstract: Embodiments of the present disclosure include techniques for calibrating analog-to-digital converters (ADCs), such as successive approximation register SAR ADCs. In one embodiment, a pattern is applied to the input of an ADC to produce digital output codes. Counts of the digital output codes are used detect errors and adjust a clock delay of a comparator in the ADC. In other embodiments, an ADC calibration circuit is coupled to a calibration algorithm executing on a remote server to calibrate one or more ADCs.

Abstract: Examples are disclosed herein that relate to automatically limiting an output current of a voltage regulator circuit responsive to detecting that the voltage regulator is in a current overload mode. In one example, a voltage regulator circuit includes an amplifier stage and a current limiter stage electrically connected to an output of the amplifier stage. The amplifier stage is configured to output a DC voltage based on a reference voltage and feedback from an output voltage. The current limiter stage is configured to operate in a quiescent mode and an overload mode. In the quiescent mode, the current limiter stage is configured to operate as a buffer stage that forms a closed feedback loop to an input of the amplifier stage. In the overload mode, the current limiter stage is configured to act as a current source that clamps an output current to a designated current.

Abstract: Examples are disclosed herein that relate to automatically limiting an output current of a voltage regulator circuit responsive to detecting that the voltage regulator is in a current overload mode. In one example, a voltage regulator circuit includes an amplifier stage and a current limiter stage electrically connected to an output of the amplifier stage. The amplifier stage is configured to output a DC voltage based on a reference voltage and feedback from an output voltage. The current limiter stage is configured to operate in a quiescent mode and an overload mode. In the quiescent mode, the current limiter stage is configured to operate as a buffer stage that forms a closed feedback loop to an input of the amplifier stage. In the overload mode, the current limiter stage is configured to act as a current source that clamps an output current to a designated current.

Abstract: Examples are provided for a multi-stage track-and-hold circuit (THA). The multi-stage THA may include a first stage, a second stage, and a third stage. The first stage may be coupled to an input signal and configured to sample the input signal. The second stage may be coupled to the first stage and may include a buffer circuit. The third stage may be coupled to the second stage and can include a bootstrapped THA. The first stage may further include a shunted source-follower circuit and a switched source-follower circuit. The shunted source-follower circuit may include a first switch that can be operable to couple an output node of the shunted source-follower circuit to ground potential.

Abstract: Examples are provided for a multi-stage track-and-hold circuit (THA). The multi-stage THA may include a first stage, a second stage, and a third stage. The first stage may be coupled to an input signal and configured to sample the input signal. The second stage may be coupled to the first stage and may include a buffer circuit. The third stage may be coupled to the second stage and can include a bootstrapped THA. The first stage may further include a shunted source-follower circuit and a switched source-follower circuit. The shunted source-follower circuit may include a first switch that can be operable to couple an output node of the shunted source-follower circuit to ground potential.

Abstract: Examples are provided for a multi-stage track-and-hold amplifier (THA). The multi-stage THA may include a first stage, a second stage, and a third stage. The first stage may be coupled to an input signal and configured to sample the input signal. The second stage may be coupled to the first stage and may include a buffer circuit. The third stage may be coupled to the second stage and can include a bootstrapped THA. The first stage may further include a shunted source-follower circuit and a switched source-follower circuit. The shunted source-follower circuit may include a first switch that can be operable to couple an output node of the shunted source-follower circuit to ground potential.

Abstract: Examples are provided for a method and apparatus for calibration of an analog-to-digital converter (ADC) including multiple sub-ADCs. The method includes applying a calibration signal to an input node of each sub-ADC. For each sub-ADC, a corresponding error signal is generated based on output signals of the sub-ADC and a reference sub-ADC. Each sub-ADC is calibrated based on the corresponding error signal. The reference sub-ADC is selected by: applying a non-zero input voltage signal to the input node of each sub-ADC, measuring a corresponding output signal of each sub-ADC in response to the non-zero input voltage signal, generating a deviation error based on a subtraction of a stored value from the measured output signal of each sub-ADC, and designating as the reference sub-ADC a sub-ADC from the multiple sub-ADCs based on the deviation error.

Abstract: Examples are provided for a method and apparatus for calibration of an analog-to-digital converter (ADC). The method includes selecting a reference sub-ADC from multiple sub-ADCs. A calibration signal is sent to an input node of each sub-ADC of the sub-ADCs. For each sub-ADC, other than the reference sub-ADC, a corresponding error signal is generated based on output signals of the sub-ADC and the reference sub-ADC. Each sub-ADC is calibrated based on the corresponding error signal. The ADC may be a time-interleaved ADC that includes the plurality of sub-ADCs, and the reference sub-ADC has a lowest relative offset among the sub-ADCs.