Abstract: A two-level skewing architecture is imposed on the memory subsystem of a volume rendering system in which voxel data is stored in mini-blocks assigned to a set of DRAM memory modules, thereby permitting data transfer at the maximum burst rate of the DRAM memory and enabling real-time volume rendering. Within each DRAM module, mini-blocks are assigned to the memory banks so that consecutively accessed mini-blocks are assigned to different banks, thereby avoiding idle cycles during data transfer and increasing DRAM transfer efficiency to nearly 100%. In one embodiment, read-out of voxel data from banks of the DRAM memory proceeds from left to right unless there is a conflict of banks, in which case the read-out order is reversed. A specialized de-skewing network is provided to re-order the voxel data read out from DRAM memory so that the voxels can be processed in the order which they are arranged in the volume data set rather than the order in which they are stored in memory.