Patents by Inventor Kenneth Creta

Kenneth Creta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070150699
    Abstract: Methods and apparatuses for firm partitioning of a computing platform.
    Type: Application
    Filed: December 28, 2005
    Publication date: June 28, 2007
    Inventors: Ioannis Schoinas, Doddaballapur Jayasimha, Eric Delano, Allen Baum, Akhilesh Kumar, Steven Chang, Suresh Chittor, Kenneth Creta, Stephen Van Doren
  • Publication number: 20060136639
    Abstract: A system, method and apparatus for prioritizing transactions is disclosed. I/O devices may generate transactions with a stream identifier. A transaction classifier may assign a priority to a transaction based upon a stream identifier of the transaction. An arbiter may select a transaction for processing based upon priorities assigned to the transaction.
    Type: Application
    Filed: December 21, 2004
    Publication date: June 22, 2006
    Inventors: William Futral, Kenneth Creta, Sujoy Sen, Gregory Cummings, Sivakumar Radhakrishnan
  • Publication number: 20060136611
    Abstract: Apparatus and method for a first device to query a second device for the availability of a hardware feature within the second device, and for the second to receive and analyze the query to determine whether or not to respond, depending on the version of hardware feature sought, a code identifying a vendor, etc., and responding with a reply providing an indication of availability of the hardware feature and/or an address at which the hardware feature may be accessed, if the determination is made to reply.
    Type: Application
    Filed: December 30, 2003
    Publication date: June 22, 2006
    Inventors: William Futral, Kenneth Creta, Sujoy Sen, Gregory Cummings, Sivakumar Radhakrishnan
  • Publication number: 20060101183
    Abstract: A technique to broadcast a message across a point-to-point network. More particularly, embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect.
    Type: Application
    Filed: November 8, 2004
    Publication date: May 11, 2006
    Inventors: Keshavan Tiruvallur, Kenneth Creta, Robert Blankenship
  • Publication number: 20060095609
    Abstract: Write-combining in a computer system that uses a push model is set forth herein. In one embodiment, the method comprises creating one or more packets having a descriptor and the data associated with detected write transactions stored in the buffer assigned to a write-combinable range in response to a flush request to flush the buffer, and sending (pushing) these packets to the network I/O device.
    Type: Application
    Filed: October 29, 2004
    Publication date: May 4, 2006
    Inventors: Sivakumar Radhakrishnan, Siva Balasubramanian, William Futral, Sujoy Sen, Gregory Cummings, Kenneth Creta, David Lee
  • Publication number: 20060059292
    Abstract: A method and an apparatus to efficiently handle read completions that satisfy a read request are disclosed. The apparatus comprises a first port to receive data that partially satisfies a read request, a second port, wherein the data is forwarded via the second port if the second port is idle, a buffer to store the data if the second port is busy, and a combiner to combine the stored data with additional data that partially satisfies the read request as the additional data is received via the first port, wherein the second port forwards the combined data when the second port is not busy.
    Type: Application
    Filed: November 8, 2005
    Publication date: March 16, 2006
    Inventors: Kenneth Creta, Sridhar Muthrasanalluar
  • Publication number: 20050289306
    Abstract: Memory read and write requests are received. The read is received in accordance with a communication protocol that has a transaction ordering rule in which a memory read cannot pass a memory write. The memory read and write requests are forwarded to the first device in accordance with another communication protocol that has a transaction ordering rule in which a memory read may pass a memory write. The forwarded memory read request is allowed to pass the forwarded memory write request whenever a relaxed ordering flag in the received read request is asserted. Other embodiments are also described and claimed.
    Type: Application
    Filed: June 28, 2004
    Publication date: December 29, 2005
    Inventors: Sridhar Muthrasanallur, Kenneth Creta
  • Patent number: 6976115
    Abstract: A method and apparatus are described for facilitating proper ordering of peer-to-peer communications between bridged bus segments. According to one embodiment of the present invention a fence command is issued when a peer-to-peer communication between devices on separate bus segments connected on the same side of a bridge is detected. The fence command is inserted into a plurality of buffers in an I/O hub corresponding to the bus segments to force temporary ordering across all pipes of the I/O hub. The hub prohibits processing of subsequent commands from a buffer once a fence command has been read from that buffer until a corresponding fence command is read from all other buffers in the plurality of buffers therby assuring proper ordering of the peer-to-peer communication.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Kenneth Creta, Jasmin Ajanovic, Joseph Bennett
  • Publication number: 20050273400
    Abstract: Systems and methods of managing transactions provide for receiving a first flush command at a first I/O hub, wherein the first flush command is dedicated to non-posted transactions. One embodiment further provides for halting an inbound ordering queue of the first I/O hub with regard to non-posted transactions in response to the first flush command and flushing a non-posted transaction from an outgoing buffer of the first I/O hub to a second I/O hub while the inbound ordering queue is halted with regard to non-posted transactions.
    Type: Application
    Filed: June 2, 2004
    Publication date: December 8, 2005
    Inventors: Robert Blankenship, Robert Greiner, Herbert Hum, Kenneth Creta, Buderya Acharya
  • Publication number: 20050262391
    Abstract: A method is described that comprises uses at least a portion of a configuration transaction address to perform a look-up into a memory. The configuration transaction is to perform a configuration function at an I/O Unit connected to an I/O segment within a link-based computing system. The look-up is to identify a component within the link-based computing system. The I/O segment is accessed through the component within the link-based computing system.
    Type: Application
    Filed: May 10, 2004
    Publication date: November 24, 2005
    Inventors: Prashant Sethi, Kenneth Creta
  • Publication number: 20050251611
    Abstract: In various embodiments, the present invention includes a method for receiving a transaction having first header information from a first peer device at a first agent of a coherent system, inserting second header information onto the transaction, and routing the transaction to a second peer device using the second header information. In one such embodiment, the first header may be a header of a first protocol and the second header may be of a different protocol that is used to tunnel the transaction through the coherent system.
    Type: Application
    Filed: April 27, 2004
    Publication date: November 10, 2005
    Inventors: Kenneth Creta, Robert Blankenship, Sridhar Muthrasanallur, Jasmin Ajanovic
  • Publication number: 20050251612
    Abstract: In one embodiment of the present invention, a method may include separating incoming transactions to an agent of a coherent system into at least a first channel, a second channel, and a third channel, based upon a type of the incoming transactions. The incoming transactions may be sent by a peer device coupled to the coherent system. By separating the transactions based on type, deadlocks may be avoided.
    Type: Application
    Filed: April 27, 2004
    Publication date: November 10, 2005
    Inventors: Kenneth Creta, Aaron Spink, Robert Blankenship
  • Publication number: 20050235067
    Abstract: Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.
    Type: Application
    Filed: April 20, 2004
    Publication date: October 20, 2005
    Inventors: Kenneth Creta, Aaron Spink, Lance Hacking, Sridhar Muthrasanallur, Jasmin Ajanovic
  • Publication number: 20050210229
    Abstract: The ability to configure an integrated device with a decoder in a processor or network component according to PCI or PCI Express interconnects.
    Type: Application
    Filed: March 22, 2004
    Publication date: September 22, 2005
    Inventors: Prashant Sethi, Kenneth Creta, Raymond Tetrick
  • Publication number: 20030188072
    Abstract: A method and apparatus are described for facilitating proper ordering of peer-to-peer communications between bridged bus segments. According to one embodiment of the present invention a fence command is issued when a peer-to-peer communication between devices on separate bus segments connected on the same side of a bridge is detected. The fence command is inserted into a plurality of buffers in an I/O hub corresponding to the bus segments to force temporary ordering across all pipes of the I/O hub. The hub prohibits processing of subsequent commands from a buffer once a fence command has been read from that buffer until a corresponding fence command is read from all other buffers in the plurality of buffers therby assuring proper ordering of the peer-to-peer communication.
    Type: Application
    Filed: March 28, 2002
    Publication date: October 2, 2003
    Inventors: Kenneth Creta, Jasmin Ajanovic, Joseph Bennett
  • Patent number: 5742831
    Abstract: Methods and apparatus for maintaining cache coherency for pending load operations. A processor is selectively stalling only when there exists certain relationships between the address of an incoming store instruction and the addresses of the pending load instructions. The address specified by an incoming store instruction is compared with all the addresses specified by the pending load instructions that are stored in a bus queue. The processor is stalled from issuing subsequent instructions and executing the store instruction if the comparison results in a match of the store instruction address with any of the addresses of the pending load instructions. Instruction issue and execution of the store instruction are unstalled when data from the matching load instruction address returns. Alternatively, a count of the number of load instructions pending in the bus queue for each specified address may be maintained.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: April 21, 1998
    Assignee: Intel Corporation
    Inventor: Kenneth Creta