Abstract: In one aspect of the embodiments, malicious instructions executed or to be executed by a processor in a computing device are identified and preventive action is taken in response to that detection, thereby preventing harm to the computing device and the user's data by the malicious instructions. In another aspect of the embodiments, a thread context monitor determines which thread are active within an operating system at any given time, which further enhances the ability to determine which thread contains malicious instructions.

Abstract: In one aspect of the embodiments, malicious instructions executed or to be executed by a processor in a computing device are identified and preventive action is taken in response to that detection, thereby preventing harm to the computing device and the user's data by the malicious instructions. In another aspect of the embodiments, a thread context monitor determines which thread are active within an operating system at any given time, which further enhances the ability to determine which thread contains malicious instructions.

Abstract: In one aspect of the embodiments, malicious instructions executed or to be executed by a processor in a computing device are identified and preventive action is taken in response to that detection, thereby preventing harm to the computing device and the user's data by the malicious instructions. In another aspect of the embodiments, a thread context monitor determines which thread are active within an operating system at any given time, which further enhances the ability to determine which thread contains malicious instructions.

Abstract: An semiconductor device including logic circuitry, a plurality of pins, and an interface unit coupling the logic circuitry to the plurality of pins, wherein the interface unit permits any of the pins to be coupled to any portion of the logic circuitry. The semiconductor device provides a template by which many different types of semiconductor devices, with varied pin assignments, can be manufactured, without the need for changing production masks.

Abstract: An semiconductor device including logic circuitry, a plurality of pins, and an interface unit coupling the logic circuitry to the plurality of pins, wherein the interface unit permits any of the pins to be coupled to any portion of the logic circuitry. The semiconductor device provides a template by which many different types of semiconductor devices, with varied pin assignments, can be manufactured, without the need for changing production masks.

Abstract: A memory paging method and apparatus using a memory paging register and a memory paging mask register. The invention has particular application in the partition of memory used by more than one software application program. The bits of the memory paging mask register selectably disable bits of the memory paging register to redefine the length and physical characteristics of pages in memory based on the needs of a software program. As a result, the paged partitions in memory may be of variable length and/or may comprise non-contiguous portions of the memory.

Abstract: An semiconductor device including logic circuitry, a plurality of pins, and an interface unit coupling the logic circuitry to the plurality of pins, wherein the interface unit permits any of the pins to be coupled to any portion of the logic circuitry. The semiconductor device provides a template by which many different types of semiconductor devices, with varied pin assignments, can be manufactured, without the need for changing production masks.

Abstract: A method of automatically detecting the baud rate of an input signal and an apparatus using the method. A counter is started upon detecting a first transition of the input signal. The counter is stopped upon detecting a second transition of the input signal. After the counter is stopped, the measured count in the counter represents the duration between the first and second transitions of the input signal. The measured count is compared to a plurality of expected counts to determine which of the plurality of expected counts has a value closest to the measured count. The input signal is sampled using a baud rate based on the expected count having a value closest to the measured count.

Abstract: A resource port that provides a host processor the facility to request, share and access the resources of data communication equipment (DCE), including the memory and I/O registers of the DCE controller. In one embodiment the resource port has a controller request line to provide the host with a facility to request access to the controller resources, and an interface circuit to provide the facility to index all the resources of the DCE. The interface circuit compensates for any disparity between the widths of the controller address bus and the host processor address bus, and between the widths of the host processor data bus and the controller data bus.

Abstract: A technique is provided for setting an error status bit in a first-in, first-out memory having data words with associated error bits. When a word having an associated error bit that is set to indicate an error is written into the FIFO, the write pointer is captured, and a flag is set, indicating that the FIFO has a word with an error. If a second word is written which has an error, that pointer value is captured, overwriting the current value. As the FIFO is read, the read pointers are compared with the captured write pointer. When the values are equal, and the FIFO is read, the flag is cleared, indicating that there are no more errors in the FIFO. In an exemplary case, each word in the FIFO has 8 data bits and 3 error bits. A FIFO used in implementing a UART in a modem typically includes 16 or 32 words.