Abstract: An arrangement for digitizing television signals, particularly the staircase portion of the vertical interval test signal transmitted by the British Broadcasting Corporation and the Independent Broadcasting Authority comprises a luminance/chrominance separator (2) and two analog to digital converters (ADC's) (6, 9). The ADC(6) digitizes the color subcarrier which has a low amplitude but a high frequency while the ADC(9) digitizes the high amplitude low frequency luminance portion. The digitized samples are stored in two sections of RAM (11, 13) under the control of a write address generator (25) and two respective write control circuits (14,17). The ADC(6) operates at 4.sub.fsc and has a resolution of 7 bits while the ADC(9) operates at one sixteenth of that rate and has a resolution of 10 bits. This enables a full 10 bit resolution to be obtained without requiring a high cost ADC.

Abstract: A frequency synthesizer includes frequency reduction means which includes a pulse swallow circuit PS which cancels cycles from the frequency Fo under the control of a rate multiplier RM. To prevent phase jitter at the output of phase comparator PC due to the cancelled cycles, a compensation signal HP is derived from a swallow command signal A and from a multiplying fraction n/x of the rate multiplier. In order to keep the DC level of the signal HP constant, the signal HP is bidirectional with respect to a mid-point voltage level and the total area of the pulses in one direction is the same as the total area of the pulses in the other direction. The invention is applicable to both phase locked loop synthesizers (FIG. 2) and direct synthesizers (FIG. 11).