Patents by Inventor Kenneth D. Van Egmond

Kenneth D. Van Egmond has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated parity-based testing for integrated circuits
    Patent number: 5193092
    Abstract: An integrated circuit includes parity chains which serve as test logic. Each parity chain has a series of XOR gates, where one input to each succeeding XOR gate in a chain is tied to the output of the preceding XOR gate. The remaining inputs are tied to nodes of the main logic, thus defining test points. An error at any one of the test points is reflected in the output of the parity chain. The outputs of the parity chains are arranged as parallel inputs to a linear feedback shift register which provides a serial signature which can be analyzed to detect integrated circuit defects.
    Type: Grant
    Filed: December 20, 1990
    Date of Patent: March 9, 1993
    Assignee: VLSI Technology, Inc.
    Inventors: Mark R. Hartoog, James A. Rowson, Robert D. Shur, Kenneth D. Van Egmond