Abstract: One variation of a method for detecting and handling falls by residents of a facility includes: receiving a notification for a fall event from a resident wearable device associated with a resident; determining a location of the resident within a facility at a time of the fall; in response to the notification, distributing a fall response prompt to a set of computing devices, each computing device associated with a care provider; in response to receipt of a fall response confirmation from a first computing device, deescalating the fall response prompt at a second computing device; and, in response to proximity of the first computing device to the resident wearable device, authorizing edit permissions for an electronic incident report by a first care provider exclusive of a second care provider.

Abstract: One variation of a method for detecting and handling falls by residents of a facility includes: receiving a notification for a fall event from a resident wearable device associated with a resident; determining a location of the resident within a facility at a time of the fall; in response to the notification, distributing a fall response prompt to a set of computing devices, each computing device associated with a care provider; in response to receipt of a fall response confirmation from a first computing device, deescalating the fall response prompt at a second computing device; and, in response to proximity of the first computing device to the resident wearable device, authorizing edit permissions for an electronic incident report by a first care provider exclusive of a second care provider.

Abstract: A method of reducing current leakage in product variants of a semiconductor device, during the fabrication of the semiconductor device. The method involves using a semiconductor process technique for reducing current leakage in semiconductor product variants having unused circuits. A semiconductor device or integrated circuit fabricated by this method has reduced current leakage upon powering as well as during operation. The method involves semiconductor process technique that substantially increases the Vt (threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors.

Abstract: A method of reducing current leakage in unused circuits performed during semiconductor fabrication and a semiconductor device or integrated circuit thereby formed. The method involves modifying a characteristic of at least one idle circuit that is unused in a product variant, to inhibit the circuit and reduce current leakage therefrom upon powering as well as during operation. The method can substantially increase the Vt (threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors. The method is also suitable for controlling other transistor parameters, such as transistor channel length, as well as other active elements, such as N-type resistors or P-type resistors, in unused circuits which affect leakage current as well as for other unused circuits, such as a high Vt circuit, a standard Vt circuit, a low Vt circuit, and an SRAM cell Vt circuit.

Abstract: A method of reducing current leakage in unused circuits performed during semiconductor fabrication and a semiconductor device or integrated circuit thereby formed. The method involves modifying a characteristic of at least one idle circuit that is unused in a product variant, to inhibit the circuit and reduce current leakage therefrom upon powering as well as during operation. The method can substantially increase the Vt (threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors. The method is also suitable for controlling other transistor parameters, such as transistor channel length, as well as other active elements, such as N-type resistors or P-type resistors, in unused circuits which affect leakage current as well as for other unused circuits, such as a high Vt circuit, a standard Vt circuit, a low Vt circuit, and an SRAM cell Vt circuit.

Abstract: An improved scan flip-flop and method of using same. The scan flip-flop has a separate dedicated scan output driven by a scan output signal driver. Scan shift race conditions are minimized by providing a weak scan output signal driver and inserting delay elements within a cell for a scan flip-flop in the scan signal path. The use of the improved scan flip-flop allows for a one-pass scan synthesis process which provides accurate flip-flop cell timing and area information during the design process.

Abstract: An improved routing system and method allow routing of pluralities of signals to circuit blocks on integrated circuit chips using minimal die area. The improved routing system employs a plurality of tri-state buffers, a plurality of conductive lines, and a controller. The circuit block can be driven from remote locations via the tri-state buffers and conductive lines. The tri-state buffers are selectively enabled one at a time by the controller to prevent signal contention. The multiplexors encountered in conventional routing systems are not needed. The improved routing system and method are ideal for routing to and from large circuit blocks which have numerous terminals, such as embedded dynamic random access memory units, embedded static random access memory units, central processing units, arithmetic logic units, register files, and cores generally.

Abstract: An integrated circuit includes a first circuit module for generating a plurality of digital signals and a second circuit module for receiving the digital signals. A multiple input signature module receives the digital signals that are received by the second circuit module. The signature module generates and stores a signature value which is indicative of data values of the digital signals over a plurality of cycles. The signature module operates in response to control circuitry, which is responsive to a test signal, to cause the values indicative of the digital signals to be stored to the multiple input signature module, each time that valid signal values are received by the second circuit module. The multiple input signature module may be used for diagnostics by capturing data at a single, predetermined cycle. The module may be initialized to a predetermined value to ensure the signature value or, the single value captured, accurately reflects the data value of the digital signals.

Abstract: A method of accurately simulating how design defects and faults are detected in the board design and manufacturing test environments is provided which uses statements in the simulation control language of a fault simulator. The simulation of the operation of electronic boards (which may not yet have been built) in their expected test environments is possible. The set of statements used in the simulation language allows the proposed functional self-test code, also called diagnostic code or power-on self-test code, which is to be executed by a (micro-)processor, to be tested for its effectiveness. The simulation must synchronize the simulated execution of the processor code to be evaluated with the fault detection by the code being evaluated, simulate the use of any attached tester, such as a logic analyzer, and provide data that can be used for programming devices in the test environment.

Abstract: A hybrid random pattern self-test approach is employed in an on-chip fashion to provide desired test signals to circuits on the chip. A simplified weighting circuit is shown to be effective even when only a single bit from a linear feedback shift register is employed for random signal generation. The reduction in linear feedback shift register size and associated weighting circuitry enables the apparatus to be much more readily usable in an on-product configuration thus resulting in significant initial and subsequent test circuit advantages.

Abstract: A memory embedded in a integrated processor chip is dynamically stressed tested by repeatedly writing a test pattern to the data locations of the memory in which a high percentage of the memory cells are sequentially written with complementary data in order to create a high stress on the memory devices. The test pattern is generated as a function of the number of address locations of the memory and the number of data bits of a memory data word. The test pattern is rotated each time the memory is addressed. The test pattern preferably has a contiguous group of digits with the number of digits in the contiguous group being a function of the number of address locations and the number of data bits in the memory word. The memory data input register is configured as a recirculating loop and additional dummy bits are added to provide recirculating loops longer than the data input register.