Abstract: A method and system of merging one-bit cells in an integrated circuit layout, comprising a database to store the layout, a placer in communication with the database to update the layout, and a merger in communication with the placer. The merger is configured to: identify a set of one-bit cells in the integrated circuit layout; determine a set of merge cells, from among the identified set of one-bit cells, to be merged into a multi-bit register, the determination of the set of merge cells being based on each merge cell being located within a merge distance from each of the other merge cells in the set of merge cells, and each merge cell sharing a clock with the other merge cells in the set of merge cells; and generate instructions to the placer for merging the set of merge cells to form the multi-bit register in the integrated circuit layout.

Abstract: The present disclosure provides systems and methods for testing an integrated circuit or device under test (DUT). A DUT of the present invention has a plurality of scan chains, a plurality of shift register elements each associated with a respective one of the scan chains, and a programmable switch matrix to configure shift register elements of a subset of the plurality of shift register elements to cause one shift register element of the subset to receive an interleaved test sequence, and to cause the interleaved test sequence to be shifted to other shift register elements in the subset, and to input deinterleaved test sequences to scan chains associated with the subset.