Patents by Inventor Kenneth Doniger

Kenneth Doniger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7234122
    Abstract: A method and apparatus calculate resistance of a three-dimensional conductor system defined by boundary faces. The resistance calculation includes (a) partitioning the three-dimensional shape into a plurality of parallelepipeds, a boundary between two parallelepipeds forms and entire face for both of the two parallelepipeds, (b) determining at least one source face and at least one sink face from among the boundary faces, a current entering the conductor system through the source face and leaving the conductor system through the sink face, (c) setting boundary conditions with respect to the current for each of the parallelepipeds, (d) calculating power for each of the parallelepipeds with the boundary conditions, (e) calculating power for the conductor system based on the power and the boundary conditions of each of the parallelepipeds, and (f) obtaining the resistance of the conductor system by minimizing dissipation of the calculated power of the conductor system.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: June 19, 2007
    Assignee: LSI Corporation
    Inventor: Kenneth Doniger
  • Publication number: 20060061373
    Abstract: A method for calculating frequency-dependent impedance in an integrated circuit (IC) having transistors coupled together by a line follows. First, partition the line into a plurality of rectangles of constant material. Then, solve for the minimum dissipated power in the plurality of rectangles. Finally, determine the frequency-dependent impedance from the minimum dissipated power.
    Type: Application
    Filed: September 21, 2004
    Publication date: March 23, 2006
    Inventors: Kenneth Doniger, William Loh
  • Publication number: 20050235235
    Abstract: A method and apparatus calculate resistance of a three-dimensional conductor system defined by boundary faces. The resistance calculation includes (a) partitioning the three-dimensional shape into a plurality of parallelepipeds, a boundary between two parallelepipeds forms and entire face for both of the two parallelepipeds, (b) determining at least one source face and at least one sink face from among the boundary faces, a current entering the conductor system through the source face and leaving the conductor system through the sink face, (c) setting boundary conditions with respect to the current for each of the parallelepipeds, (d) calculating power for each of the parallelepipeds with the boundary conditions, (e) calculating power for the conductor system based on the power and the boundary conditions of each of the parallelepipeds, and (f) obtaining the resistance of the conductor system by minimizing dissipation of the calculated power of the conductor system.
    Type: Application
    Filed: January 10, 2005
    Publication date: October 20, 2005
    Inventor: Kenneth Doniger
  • Patent number: 6802047
    Abstract: A variational method is used for calculating resistance of a conductor layer for an integrated circuit design, the conductor layer having a geometric shape defined by boundary edges. The method includes (a) partitioning the geometric shape into a plurality of rectangular regions, (b) determining at least one source edge and at least one sink edge from among the boundary edges, a current entering the conductor layer through the source edge(s) and leaving the conductor layer through the sink edge(s), (c) setting boundary conditions with respect to the current for each of the rectangular regions, (d) calculating power for each of the rectangular regions with the boundary conditions, (e) calculating power for the conductor layer based on the power and the boundary conditions of each of the rectangular regions, and (f) obtaining the resistance of the conductor layer by minimizing the power dissipation of the conductor layer.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: October 5, 2004
    Assignee: LSI Logic Corporation
    Inventor: Kenneth Doniger