Patents by Inventor Kenneth E. Bean
Kenneth E. Bean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 5250445Abstract: A semiconductor wafer (32) is patterned to have gettering areas (36-38) selectively positioned proximate devices (44-46) which require gettering. The areas (36-38) comprise germanium-doped silicon having a germanium concentration of approximately 1.5%-2.0%. The germanium creates a lattice mismatch between the substrate (32) and an epitaxial layer (34) which is sufficient to produce defects capable of gettering contaminants. The gettering areas (36-38) may be formed by selective deposition, selective etching, ion-implantation or selective diffusion techniques.Type: GrantFiled: January 17, 1992Date of Patent: October 5, 1993Assignee: Texas Instruments IncorporatedInventors: Kenneth E. Bean, Satwinder S. Malhi, Walter R. Runyan
-
Patent number: 5196378Abstract: The invention relates to a method of scribing and separating dice from each other after fabrication in a semiconductor wafer in a manner such that active circuit regions in the dice reside as near to an edge of a die as possible. The wafer is anistropically etched through the active layer and into the substrate through an opening in the mask to form a generally V-shaped channel with the dice then being separated along a vertex of the channel. The dice are then positioned to abut each other in the form of a mosaic.Type: GrantFiled: March 25, 1991Date of Patent: March 23, 1993Assignee: Texas Instruments IncorporatedInventors: Kenneth E. Bean, John Powell, Jack W. Freeman, Robert D. McGrath
-
Patent number: 5089428Abstract: A method for preparing a germanium layer (22) adjacent to a germanium silicon layer (20). Initially, a P-germanium silicon layer (16) is deposited on to an N-germanium silicon layer (14). The continuous germanium layer (22) is formed by heating the layers (14 and 16) in a steam oxidation step to approximately 1000 degrees Centigrade to transform the P-germanium silicon layer (16) into the P-germanium layer (18) and a SiO.sub.2 layer (22). A method for forming a heterojunction bipolar transistor utilizing a P-germanium layer (50) is also disclosed.Type: GrantFiled: December 27, 1989Date of Patent: February 18, 1992Assignee: Texas Instruments IncorporatedInventors: Douglas P. Verret, Kenneth E. Bean
-
Patent number: 5031072Abstract: A baseboard for orthogonal mounting of integrated circuit chips thereto is described. Plural channels (14) are anisotropically etched in a silicon baseboard (10). A corresponding plurality of integrated circuit chips (12) are inserted into the channels (14). A number of baseboard contact pads (18) are formed adjacent each channel (14), and are solder bonded to corresponding chip conductor pads (16). Interconnect conductors (20, 28) provide connection of each baseboard pad (18) either to other chips (12) or to connector pads (22) located adjacent an edge (26) of the baseboard chip mount (10). A coating (30) of silicon carbide over the surface of the baseboard chip mount (10) improves the thermal efficiency of the assembly.Type: GrantFiled: January 31, 1990Date of Patent: July 9, 1991Assignee: Texas Instruments IncorporatedInventors: Satwinder S. Malhi, Kenneth E. Bean
-
Patent number: 4982263Abstract: A silicon on insulator semiconductor structure employs a strain layer fabricated of an electrically inactive material. The strain layer comprises silicon with a germanium additive to produce a sublayer exhibiting a low breakdown voltage and thus effective for selective anodization.Type: GrantFiled: March 10, 1989Date of Patent: January 1, 1991Assignee: Texas Instruments IncorporatedInventors: David B. Spratt, Eldon J. Zorinsky, Robert L. Virkus, Kenneth E. Bean, Richard L. Yeakley
-
Patent number: 4922378Abstract: A baseboard for orthogonal mounting of integrated circuit chips is described. Plural channels (14) are anisotropically etched in a silicon baseboard (10). A corresponding plurality of integrated circuit chips (12) are inserted into the channels (14). A number of baseboard contact pads (18) are formed adjacent each channel (14), and are solder bonded to corresponding chip conductor pads (16). Interconnect conductors (20, 28) provide connection of each baseboard pad (18) either to other chips (12) or to connector pads (22) located adjacent an edge (26) of the baseboard chip mount (10). A coating (30) of silicon carbide over the surface of the baseboard chip mount (10) improves the thermal efficiency of the assembly.Type: GrantFiled: August 1, 1986Date of Patent: May 1, 1990Assignee: Texas Instruments IncorporatedInventors: Satwinder S. Malhi, Kenneth E. Bean
-
Patent number: 4875086Abstract: Preferred embodiments include silicon-on-insulator structures (30) and integrated circuits include a thin single crystal silicon layer (32) on a silicon dioxide layer (34) which is on a polysilicon layer (36) bonded to a surface-oxidized silicon substrate (42) by a glass layer (38). Also, single crystal silicon layers on oxide on polysilicon substrates and methods of fabrication are included in the preferred embodiments.Type: GrantFiled: May 22, 1987Date of Patent: October 17, 1989Assignee: Texas Instruments IncorporatedInventors: Satwinder D. S. Malhi, Chi-Cheong Shen, Kenneth E. Bean, Peng-Heng Chang
-
Patent number: 4855809Abstract: An orthogonal chip mount system module (10) comprising a base module (12), an interconnect chip (14), orthogonal slots (16) and semiconductor chips (18) is provided. The interconnect chip (14) is fixed to the base module (12) by high thermal conductivity epoxy. The semiconductor chips (18) are interference fitted into the slots (16). Solder pads (20) on the semiconductor chips (18) are aligned with solder pads (22) on the interconnect chip (14) and the system module (10) is then heated to the reflow temperature of the solder forming joints (24).Type: GrantFiled: November 24, 1987Date of Patent: August 8, 1989Assignee: Texas Instruments IncorporatedInventors: Satwinder Malhi, Kenneth E. Bean, Charles C. Driscoll, Pallab K. Chatterjee
-
Patent number: 4849370Abstract: A silicon on insulator semiconductor structure employs a strain layer fabricated of an electrically inactive material. The strain layer comprises silicon with a germanium additive to produce a sublayer exhibiting a low breakdown voltage and thus effective for selective anodization.Type: GrantFiled: December 21, 1987Date of Patent: July 18, 1989Assignee: Texas Instruments IncorporatedInventors: David B. Spratt, Eldon J. Zorinsky, Robert L. Virkus, Kenneth E. Bean, Richard L. Yeakley
-
Patent number: 4737470Abstract: The disclosure relates to a three dimensional semiconductor structure formed in a semiconductor substrate wherein electrical components, both active and passive, are formed on the substrate surface as well as in grooves formed in the substrate at an angle and extending to the surface. The substrate surface is designed to lie in a predetermined crystallographic plane of the substrate material and the grooves extend in a predetermined crystallographic direction from said plane, this being accomplished by orientation dependent etching.Type: GrantFiled: September 12, 1986Date of Patent: April 12, 1988Assignee: Texas Instruments IncorporatedInventor: Kenneth E. Bean
-
Patent number: 4663648Abstract: The disclosure relates to a three dimensional semiconductor structure formed in a semiconductor substrate wherein electrical components, both active and passive, are formed on the substrate surface as well as in grooves formed in the substrate at an angle and extending to the surface. The substrate surface is designed to lie in a predetermined crystallographic plane of the substrate material and the grooves extend in a predetermined crystallographic direction from said plane, this being accomplished by orientation dependent etching.Type: GrantFiled: December 19, 1984Date of Patent: May 5, 1987Assignee: Texas Instruments IncorporatedInventor: Kenneth E. Bean
-
Patent number: 4599247Abstract: The disclosure relates to a method of growing thermal oxide on silicon wherein the oxide is grown at an increased rate, at reduced temperature or a combination thereof. This is accomplished by operating in an hermetic quartz tube capable of withstanding high pressure with steam or oxygen at super atmospheric pressure.Type: GrantFiled: January 4, 1985Date of Patent: July 8, 1986Assignee: Texas Instruments IncorporatedInventors: Kenneth E. Bean, Robert H. Havemann, Andrew Lane
-
Patent number: 4063271Abstract: Disclosed are improved field-effect and bipolar semiconductor devices and the method of making them, wherein maximum junction control provides highly predictable device parameters. Low temperature epitaxial depositions provide tight junction thickness and resistivity control, and an orientation dependent etch forms grooves circumscribing portions of the host substrate and overlying epitaxial layers to provide dielectrically isolated single crystalline mesas utilized in forming electronic devices.Type: GrantFiled: July 26, 1972Date of Patent: December 13, 1977Assignee: Texas Instruments IncorporatedInventors: Kenneth E. Bean, William W. Lloyd
-
Patent number: 4050979Abstract: This disclosure relates to methods of producing thin layers of silicon as well as thin layers of silicon on insulating substrates such as silicon dioxide or polycrystalline silicon by forming either an n- layer of single crystal silicon over a p++ layer of single crystal silicon or a p- layer of single crystal silicon over an n++ layer of single crystal silicon and then removing either the n++ or p++ single crystal substrate, as the case may be, by utilizing an etch which will only etch the n++ or p++ region and will stop when the n- or p- region, as the case may be, has been reached.Type: GrantFiled: January 14, 1976Date of Patent: September 27, 1977Assignee: Texas Instruments IncorporatedInventors: Ronald K. Smeltzer, Kenneth E. Bean
-
Patent number: 3989946Abstract: This disclosure defines an infrared image detector formed in a block of semiconductor material by etching slots in the semiconductor material. The slots define the individual detectors, effectively isolate them from each other both optically and electrically, and permit the detectors to be placed very close to each other.Type: GrantFiled: March 31, 1975Date of Patent: November 2, 1976Assignee: Texas Instruments IncorporatedInventors: Richard A. Chapman, Kenneth E. Bean
-
Patent number: 3969749Abstract: Process permitting control of the thickness of the thin layer of semiconductor material by first forming a slot of a predetermined depth in one surface so that the slot will be exposed during removal of material from the opposite surface should the thickness of the thin layer of semiconductor material become less than the depth of the slot, and a (110) oriented semiconductor substrate having a slot formed therein which is bounded by converging {111} planes.In a preferred embodiment the thickness control is realized by first preparing the slice of semiconductor material so that at least one of its surfaces has a (100) orientation. There is then formed on the surface of the slice having the (100) orientation an etch-resistant mask having a window opened therethrough such that the window defines on the surface of the slice two lines which are parallel to each other and to lines defined by the intersection of {111} planes with the surface of the slice.Type: GrantFiled: May 19, 1975Date of Patent: July 13, 1976Assignee: Texas Instruments IncorporatedInventor: Kenneth E. Bean
-
Patent number: 3936929Abstract: Disclosed are improved field-effect and bipolar semiconductor devices and the method of making them, wherein maximum junction control provides highly predictable device parameters. Low temperature epitaxial depositions provide tight junction thickness and resistivity control, and an orientation dependent etch forms grooves circumscribing portions of the host substrate and overlying epitaxial layers to provide dielectrically isolated single crystalline mesas utilized in forming electronic devices.This is a division of application Ser. No. 275,116, filed July 26, 1972.Type: GrantFiled: June 26, 1974Date of Patent: February 10, 1976Assignee: Texas Instruments IncorporatedInventors: Kenneth E. Bean, William W. Lloyd