Abstract: A graphics processing unit is operable to execute graphics processing programs comprising sequences of instructions to perform graphics processing operations. The graphics processing unit includes execution processing circuitry operable to execute instructions to perform graphics processing operations and instruction issuing circuitry operable to issue instructions to be executed to the execution processing circuitry. The graphics processing unit also includes energy management circuitry operable to monitor the energy usage by the execution processing circuitry when executing instructions, determine, based on the monitoring of the energy usage, a permitted energy usage range for the execution processing circuitry when executing instructions for a future time period, and control the issuing of instructions to the execution processing circuitry by the instruction issuing circuitry during the future time period based on the permitted energy usage range determined for the future time period.

Abstract: A graphics processing apparatus comprises fragment generating circuitry to generate graphics fragments corresponding to graphics primitives, thread processing circuitry to perform threads of processing corresponding to the fragments, and forward kill circuitry to trigger a forward kill operation to prevent further processing of a target thread of processing corresponding to an earlier graphics fragment when the forward kill operation is enabled for the target thread and the earlier graphics fragment is determined to be obscured by one or more later graphics fragments. The thread processing circuitry supports enabling of the forward kill operation for a thread including at least one forward kill blocking instruction having a property indicative that the forward kill operation should be disabled for the given thread, when the thread processing circuitry has not yet reached a portion of the thread including the at least one forward kill blocking instruction.

Abstract: A data processor in which execution threads may be grouped together into thread groups in which the plural threads of a thread group can each execute a set of instructions in lockstep, one instruction at a time. The data processor comprises a plurality of execution lanes for executing respective execution threads of a thread group. For each thread group in a pool 51 of thread groups available to be issued to the execution lanes, an indication 54 of the active threads of the thread group is stored, and sets of at least one thread group from the pool 51 of available thread groups to issue 73 to the execution lanes for execution are selected 72 based on the indications of the active threads for the thread groups in the thread group pool.

Abstract: A graphics processing unit is operable to execute graphics processing programs comprising sequences of instructions to perform graphics processing operations. The graphics processing unit includes execution processing circuitry operable to execute instructions to perform graphics processing operations and instruction issuing circuitry operable to issue instructions to be executed to the execution processing circuitry. The graphics processing unit also includes energy management circuitry operable to monitor the energy usage by the execution processing circuitry when executing instructions, determine, based on the monitoring of the energy usage, a permitted energy usage range for the execution processing circuitry when executing instructions for a future time period, and control the issuing of instructions to the execution processing circuitry by the instruction issuing circuitry during the future time period based on the permitted energy usage range determined for the future time period.

Abstract: A data processor in which execution threads may be grouped together into thread groups in which the plural threads of a thread group can each execute a set of instructions in lockstep, one instruction at a time. The data processor comprises a plurality of execution lanes for executing respective execution threads of a thread group. For each thread group in a pool 51 of thread groups available to be issued to the execution lanes, an indication 54 of the active threads of the thread group is stored, and sets of at least one thread group from the pool 51 of available thread groups to issue 73 to the execution lanes for execution are selected 72 based on the indications of the active threads for the thread groups in the thread group pool.

Abstract: A program is analyzed to identify instructions that will load external data and to determine whether such instructions are followed by a sequence of instructions that will produce the same result for each thread in a thread group if the data loaded by the load instruction is the same for each thread in the thread group. Each time there is an external load instruction, it is determined whether the data loaded by the external load instruction is the same for all threads of the thread group, and whether the external load instruction was indicated as being followed by a sequence of instructions that produce the same result if the external load instruction loads the same data value for each thread of a thread group. The subsequent instructions are then executed for only a single thread of the thread group, or for all the threads of the thread group.

Abstract: A graphics processing apparatus comprises fragment generating circuitry to generate graphics fragments corresponding to graphics primitives, thread processing circuitry to perform threads of processing corresponding to the fragments, and forward kill circuitry to trigger a forward kill operation to prevent further processing of a target thread of processing corresponding to an earlier graphics fragment when the forward kill operation is enabled for the target thread and the earlier graphics fragment is determined to be obscured by one or more later graphics fragments. The thread processing circuitry supports enabling of the forward kill operation for a thread including at least one forward kill blocking instruction having a property indicative that the forward kill operation should be disabled for the given thread, when the thread processing circuitry has not yet reached a portion of the thread including the at least one forward kill blocking instruction.

Abstract: In a data processing system, a program to be executed by a programmable processing unit of the data processing system is analyzed to identify a sequence of instructions that would produce the same result for plural execution threads were those plural execution threads each to execute the sequence of instructions using the same input data. Then, when the program is being executed, when an execution thread is to execute the identified sequence of instructions, it is determined whether a result produced by an earlier execution thread executing the sequence of instructions, and that used the same input data, is stored in memory or not. The current thread then either executes the sequence of instructions, or retrieves the stored result produced by the earlier execution of the sequence of instructions and skips execution of the sequence of instructions for which the result is stored, accordingly.

Abstract: A graphics processing unit 3 includes a rasterizer 25, a thread spawner 40, a programmable execution unit 41, a varying interpolator 42, a texture mapper 43, and a blender 29. The programmable execution unit 41 is able to communicate with the varying interpolator 42, the texture mapper 43 and the blender 29 to request processing operations by those graphic specific accelerators. In addition to this, these graphics-specific accelerators are also able to communicate directly with each other and with the thread spawner 40, independently of the programmable execution unit 41. This allows for certain graphics processing operations to be performed using direct communication between the graphics-specific accelerators of the graphics processing unit, instead of executing instructions in the programmable execution unit to trigger the performance of those operations by the graphics-specific accelerators.

Abstract: A program is analysed to identify instructions that will load external data and to determine whether such instructions are followed by a sequence of instructions that will produce the same result for each thread in a thread group if the data loaded by the load instruction is the same for each thread in the thread group. Each time there is an external load instruction, it is determined whether the data loaded by the external load instruction is the same for all threads of the thread group, and whether the external load instruction was indicated as being followed by a sequence of instructions that produce the same result if the external load instruction loads the same data value for each thread of a thread group. The subsequent instructions are then executed for only a single thread of the thread group, or for all the threads of the thread group.

Abstract: A graphics processing unit 3 includes a rasteriser 25, a thread spawner 40, a programmable execution unit 41, a varying interpolator 42, a texture mapper 43, and a blender 29. The programmable execution unit 41 is able to communicate with the varying interpolator 42, the texture mapper 43 and the blender 29 to request processing operations by those graphic specific accelerators. In addition to this, these graphics-specific accelerators are also able to communicate directly with each other and with the thread spawner 40, independently of the programmable execution unit 41. This allows for certain graphics processing operations to be performed using direct communication between the graphics-specific accelerators of the graphics processing unit, instead of executing instructions in the programmable execution unit to trigger the performance of those operations by the graphics-specific accelerators.

Abstract: A method and apparatus includes primitive setup circuitry for determining a plurality of functions for an input graphics primitive, including an edge function associated with each edge of the input graphics primitive and a depth function associated with the input graphics primitive. Rasterization circuitry performs a rasterization operation in order to calculate position data for a plurality of graphics fragments to be used to represent the input graphics primitive. In a default mode of operation, depth bound clipping circuitry performs a depth bound clipping operation by determining, for each graphics fragment in said plurality of graphics fragments, a depth value for said graphics fragment using the depth function, and determining whether said depth value resides within a valid depth range of a view frustum, the graphics fragment being discarded from further processing if its depth value does not reside within said valid depth range.

Abstract: A method and apparatus includes primitive setup circuitry for determining a plurality of functions for an input graphics primitive, including an edge function associated with each edge of the input graphics primitive and a depth function associated with the input graphics primitive. Rasterization circuitry performs a rasterization operation in order to calculate position data for a plurality of graphics fragments to be used to represent the input graphics primitive. In a default mode of operation, depth bound clipping circuitry performs a depth bound clipping operation by determining, for each graphics fragment in said plurality of graphics fragments, a depth value for said graphics fragment using the depth function, and determining whether said depth value resides within a valid depth range of a view frustum, the graphics fragment being discarded from further processing if its depth value does not reside within said valid depth range.