Patents by Inventor Kenneth Edward Beilstein, Jr.
Kenneth Edward Beilstein, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6174763Abstract: A three-dimensional five transistor SRAM trench structure and fabrication method therefor are set forth. The SRAM trench structure includes four field-effect transistors (“FETs”) buried within a single trench. Specifically, two FETs are located at each of two sidewalls of the trench with one FET being disposed above the other FET at each sidewall. Coaxial wiring electrically cross-couples the FETs within the trench such that a pair of cross-coupled inverters comprising the storage flip-flop for the SRAM cell is formed, A fifth, I/O transistor is disposed at the top of the trench structure, and facilitates access to the flip-flop. Specific details of the SRAM trench structure, and fabrication methods therefor are also set forth.Type: GrantFiled: January 6, 1997Date of Patent: January 16, 2001Assignee: International Business Machines CorporationInventors: Kenneth Edward Beilstein, Jr., Claude Louis Bertin, John Edward Cronin, Francis Roger White
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Patent number: 5923181Abstract: Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring.Type: GrantFiled: April 24, 1997Date of Patent: July 13, 1999Assignee: International Business Machine CorporationInventors: Kenneth Edward Beilstein, Jr., Claude Louis Bertin, Dennis Charles Dubois, Wayne John Howell, Gordon Arthur Kelley, Jr., Christopher Paul Miller, David Jacob Perlman, Gustav Schrottke, Edmund Juris Sprogis, Jody John VanHorn
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Semiconductor chip kerf clear method for forming semiconductor chips and electronic module therefore
Patent number: 5804464Abstract: A fabrication method including a semiconductor chip kerf clear process and a resulting semiconductor chip and electronic module formed thereby. The fabrication method includes providing a wafer comprising a plurality of integrated circuit chips having kerf regions between them. Chip metallization is present within the kerf regions. A photolithography process is used to protect the wafer exposing only the kerf regions. Next, the wafer is etched, clearing the chip metallization from the kerf regions. The wafer is then diced and the chips are stacked to form a monolithic electronic module. A side surface of the electronic module is processed to expose transfer metals extending thereto, thereby facilitating electrical connection to the chips within the electronic module. Specific details of the fabrication method, resulting integrated circuit chips and monolithic electronic module are set forth.Type: GrantFiled: May 1, 1997Date of Patent: September 8, 1998Assignee: International Business Machines CorporationInventors: Kenneth Edward Beilstein, Jr., Claude Louis Bertin, Timothy Harrison Daubenspeck, Wayne John Howell -
Patent number: 5786628Abstract: A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.Type: GrantFiled: October 16, 1997Date of Patent: July 28, 1998Assignee: International Business Machines CorporationInventors: Kenneth Edward Beilstein, Jr., Claude Louis Bertin, John Edward Cronin, Wayne John Howell, James Marc Leas, David Jacob Perlman
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Patent number: 5719438Abstract: A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.Type: GrantFiled: June 6, 1995Date of Patent: February 17, 1998Assignee: International Business Machines CorporationInventors: Kenneth Edward Beilstein, Jr., Claude Louis Bertin, John Edward Cronin, Wayne John Howell, James Marc Leas, David Jacob Perlman
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Patent number: 5686843Abstract: Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring.Type: GrantFiled: June 30, 1995Date of Patent: November 11, 1997Assignee: International Business Machines CorporationInventors: Kenneth Edward Beilstein, Jr., Claude Louis Bertin, Dennis Charles Dubois, Wayne John Howell, Gordon Arthur Kelley, Jr., Christopher Paul Miller, David Jacob Perlman, Gustav Schrottke, Edmund Juris Sprogis, Jody John VanHorn
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Patent number: 5670803Abstract: A three-dimensional five transistor SRAM trench structure and fabrication method therefor are set forth. The SRAM trench structure includes four field-effect transistors ("FETs") buried within a single trench. Specifically, two FETs are located at each of two sidewalls of the trench with one FET being disposed above the other FET at each sidewall. Coaxial wiring electrically cross-couples the FETs within the trench such that a pair of cross-coupled inverters comprising the storage flip-flop for the SRAM cell is formed. A fifth, I/O transistor is disposed at the top of the trench structure, and facilitates access to the flip-flop. Specific details of the SRAM trench structure, and fabrication methods therefor are also set forth.Type: GrantFiled: February 8, 1995Date of Patent: September 23, 1997Assignee: International Business Machines CorporationInventors: Kenneth Edward Beilstein, Jr., Claude Louis Bertin, John Edward Cronin, Francis Roger White
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Patent number: 5670428Abstract: A fabrication method including a semiconductor chip kerf clear process and a resulting semiconductor chip and electronic module formed thereby. The fabrication method includes providing a wafer comprising a plurality of integrated circuit chips having kerf regions between them. Chip metallization is present within the kerf regions. A photolithography process is used to protect the wafer exposing only the kerf regions. Next, the wafer is etched, clearing the chip metallization from the kerf regions. The wafer is then diced and the chips are stacked to form a monolithic electronic module. A side surface of the electronic module is processed to expose transfer metals extending thereto, thereby facilitating electrical connection to the chips within the electronic module. Specific details of the fabrication method, resulting integrated circuit chips and monolithic electronic module are set forth.Type: GrantFiled: April 13, 1995Date of Patent: September 23, 1997Assignee: International Business Machines CorporationInventors: Kenneth Edward Beilstein, Jr., Claude Louis Bertin, Timothy Harrison Daubenspeck, Wayne John Howell
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Patent number: 5644162Abstract: A fabrication method including a semiconductor chip kerf clear process and a resulting semiconductor chip and electronic module formed thereby. The fabrication method includes providing a wafer comprising a plurality of integrated circuit chips having kerf regions between them. Chip metallization is present within the kerf regions. A photolithography process is used to protect the wafer exposing only the kerf regions. Next, the wafer is etched, clearing the chip metallization from the kerf regions. The wafer is then diced and the chips are stacked to form a monolithic electronic module. A side surface of the electronic module is processed to expose transfer metals extending thereto, thereby facilitating electrical connection to the chips within the electronic module. Specific details of the fabrication method, resulting integrated circuit chips and monolithic electronic module are set forth.Type: GrantFiled: June 10, 1996Date of Patent: July 1, 1997Assignee: International Business Machines CorporationInventors: Kenneth Edward Beilstein, Jr., Claude Louis Bertin, Timothy Harrison Daubenspeck, Wayne John Howell
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Patent number: 4092548Abstract: A load device characteristic is improved for a static inverter by reducing the load device threshold voltage as the output voltage increases from its initial value. The circuit structure to accomplish this is an isolated substrate within which the FET load device is located, that substrate being connected to an inverter circuit for raising the voltage of the substrate as the source potential increases for the preferred depletion mode load device. The particular circuit is a two-stage inverter, the first stage being a modulating signal source, the output of the first stage inverter being connected to the isolated substrate of the FET load for a second inverter, so that the FET load device for the second stage inverter has its substrate modulated so that the magnitude of the substrate potential changes at a faster rate than does the source potential.Type: GrantFiled: March 15, 1977Date of Patent: May 30, 1978Assignee: International Business Machines CorporationInventors: Kenneth Edward Beilstein, Jr., Harish Narandas Kotecha