Abstract: The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly, a method of temporarily bonding a semiconductor wafer to a wafer carrier with a multi-layered contact layer as well as a structure. A method is disclosed that includes: forming a first layer on a surface of a semiconductor wafer; forming a second layer on the first layer; bonding a perforated carrier to the second layer; and removing the semiconductor wafer from the perforated carrier. The first layer may be composed of an adhesive. The second layer may be composed of a material having a higher outgassing temperature than the first layer.

Abstract: A handle wafer which prevents edge cracking during a thinning process and method of using the handle wafer for grinding processes are disclosed. The handle wafer includes a body portion with a bottom surface. A square edge portion is provided about a circumference of the bottom surface.

Abstract: A handle wafer which prevents edge cracking during a thinning process and method of using the handle wafer for grinding processes are disclosed. The handle wafer includes a body portion with a bottom surface. A square edge portion is provided about a circumference of the bottom surface.

Abstract: The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly, a method of temporarily bonding a semiconductor wafer to a wafer carrier with a multi-layered contact layer as well as a structure. A method is disclosed that includes: forming a first layer on a surface of a semiconductor wafer; forming a second layer on the first layer; bonding a perforated carrier to the second layer; and removing the semiconductor wafer from the perforated carrier. The first layer may be composed of an adhesive. The second layer may be composed of a material having a higher outgassing temperature than the first layer.

Abstract: A backside metal ground plane with improved metal adhesion and methods of manufacture are disclosed herein. The method includes forming at least one through silicon via (TSV) in a substrate. The method further includes forming an oxide layer on a backside of the substrate. The method further includes forming a metalized ground plane on the oxide layer and in electrical contact with an exposed portion of the at least one TSV.

Abstract: Apparatus and methods modulate the bowing of thin wafers. According to a method, a wafer is formed of semiconductor material. The wafer has a front side and a back side. A cross-section of the wafer is reduced by thinning material from the front side of the wafer. A plurality of circuits comprising individual semiconductor devices are formed on the front side of the wafer. A stress-balancing layer is formed on the back side of the wafer. The stress-balancing layer comprises at least one of a polymer film and/or a metal film having at least one metal layer. A heat treatment is applied to the wafer. The heat treatment may be an annealing process to a temperature between 150° C. and 450° C., which develops an in-situ bilateral tensile stress in the stress-balancing layer that modulates the bowing of thin wafers.

Abstract: A backside metal ground plane with improved metal adhesion and methods of manufacture are disclosed herein. The method includes forming at least one through silicon via (TSV) in a substrate. The method further includes forming an oxide layer on a backside of the substrate. The method further includes forming a metalized ground plane on the oxide layer and in electrical contact with an exposed portion of the at least one TSV.

Abstract: A patterned backside metal ground plane for improved metal adhesion and methods of manufacture are disclosed herein. The method includes forming at least one die on a substrate. The at least one die is formed adjacent to a dicing channel and includes through silicon vias (TSVs). The method further includes forming a metalized ground plane on a backside of the substrate in contact with the TSVs and which is located in such areas on the backside of the substrate that it does not interfere with dicing operations performed within the dicing channel.

Abstract: Silicon-on-insulator (SOI) structures and related methods of forming such structures. In one case, a method includes providing a silicon-on-insulator (SOI) handle substrate having: a substantially uniform resistivity profile along a depth of the handle substrate; and an interstitial oxygen (Oi) concentration of less than approximately 10 parts per million atoms (ppma). The method further includes counter-doping a surface region of the handle, causing the surface region to have a resistivity greater than approximately 3 kOhm-cm, and joining the surface region of the handle substrate with a donor wafer.

Abstract: Silicon-on-insulator (SOI) structures and related methods of forming such structures. In one case, a method includes providing a silicon-on-insulator (SOI) handle substrate having: a substantially uniform resistivity profile along a depth of the handle substrate; and an interstitial oxygen (Oi) concentration of less than approximately 10 parts per million atoms (ppma). The method further includes counter-doping a surface region of the handle, causing the surface region to have a resistivity greater than approximately 3 kOhm-cm, and joining the surface region of the handle substrate with a donor wafer.

Abstract: An apparatus and method are provided for removing contaminate particulate matter from substrate surfaces such as semiconductor wafers. The method and apparatus use a material, preferably a liquid curable polymer, which is applied as a sacrificial coating to the surface of a substrate containing contaminate particulate matter thereon. An energy source is used to dislodge the contaminate particulate matter from the surface of the wafer into the sacrificial coating so that the particles are partially or fully encapsulated and suspended in the sacrificial coating. The sacrificial coating is then removed. The coating is preferably formed into a film to facilitate removal of the coating by pulling (stripping) the film providing a cleaner substrate surface.

Abstract: An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.

Abstract: A method for preparing a workpiece surface utilizing two more fluids of differing density and miscibility which create one or more fluid interfaces wherein the fluids are chosen such that the solubility or affinity of one of the fluids is high for a material to be removed from the workpiece surface while the other fluid has a low solubility or affinity for the material to be removed. The workpiece surface is treated by passing the workpiece through the fluid interface. The two or more fluids are preferably dispensed into an apparatus and allowed to settle into two or more predominant layers separated by an interface. Surface preparation techniques which may benefit from the present invention include etching, cleaning or drying processes and the like.

Abstract: An apparatus and method are provided for removing contaminate particulate matter from substrate surfaces such as semiconductor wafers. The method and apparatus use a material, preferably a liquid curable polymer, which is applied as a sacrificial coating to the surface of a substrate containing contaminate particulate matter thereon. An energy source is used to dislodge the contaminate particulate matter from the surface of the wafer into the sacrificial coating so that the particles are partially or fully encapsulated and suspended in the sacrificial coating. The sacrificial coating is then removed. The coating is preferably formed into a film to facilitate removal of the coating by pulling (stripping) the film providing a cleaner substrate surface.

Abstract: An apparatus and method are provided for removing contaminate particulate matter from substrate surfaces such as semiconductor wafers. The method and apparatus use a material, preferably a liquid curable polymer, which is applied as a sacrificial coating to the surface of a substrate containing contaminate particulate matter thereon. An energy source is used to dislodge the contaminate particulate matter from the surface of the wafer into the sacrificial coating so that the particles are partially or fully encapsulated and suspended in the sacrificial coating. The sacrificial coating is then removed. The coating is preferably formed into a film to facilitate removal of the coating by pulling (stripping) the film providing a cleaner substrate surface.

Abstract: An apparatus and method are provided for removing contaminate particulate matter from substrate surfaces such as semiconductor wafers. The method and apparatus use a material, preferably a liquid curable polymer, which is applied as a sacrificial coating to the surface of a substrate containing contaminate particulate matter thereon. An energy source is used to dislodge the contaminate particulate matter from the surface of the wafer into the sacrificial coating so that the particles are partially or fully encapsulated and suspended in the sacrificial coating. The sacrificial coating is then removed. The coating is preferably formed into a film to facilitate removal of the coating by pulling (stripping) the film providing a cleaner substrate surface.