Abstract: IC chips for photonics applications are disclosed. An example IC chip includes a substrate, an optical component above the substrate, and a first connection level above the substrate. The first connection level includes the optical component and a first cladding structure, in which the optical component is covered by the first cladding structure. The IC chip also includes a second connection level on the first connection level. The second connection level includes a first interlayer dielectric material. The IC chip further includes a second cladding structure directly above the optical component. The second cladding structure has at least a section within the second connection level. The second cladding structure is on the first cladding structure. The second cladding structure is laterally adjacent to and in direct contact with the first interlayer dielectric material. The second cladding structure includes a material different from the first interlayer dielectric material.

Abstract: Disclosed is a photonic structure and associated method. The structure includes a closed-curve waveguide having a first height, as measured from the top surface of an insulator layer, and an outer curved sidewall that extends essentially vertically the full first height (e.g., to minimize signal loss). The structure includes a closed-curve thermal coupler and a heating element. The closed-curve thermal coupler is thermally coupled to and laterally surrounded by the closed-curve waveguide and has a second height that is less than the first height. In some embodiments, the closed-curve waveguide and the closed-curve thermal coupler are continuous portions of the same semiconductor layer having different thicknesses. The heating element is thermally coupled to the closed-curve thermal coupler and thereby indirectly thermally coupled to the closed-curve waveguide.

Abstract: Disclosed is a method and structure for forming a silicide on a silicon material. The invention places the silicon material in a vacuum environment, forms metal on the silicon material, and then heats the silicon surface and the metal without breaking the vacuum environment. The processes of forming the metal and heating the silicon can be performed simultaneously without breaking the vacuum environment to form the silicide as the metal is being deposited. After the foregoing processing, the invention can remove the silicon surface from the vacuum environment and perform additional heating of the silicon surface. The first heating process forms a monosilicide and the additional heating forms a disilicide.

Abstract: The integrity of a liner in an interconnect structure or other layer in an integrate circuit is tested in a short time by exposing the liner to a reactive gas that attacks the underlying silicon or other material behind the liner. A weak spot in the liner permits the gas to react with the silicon, which produces a visible area that can be readily identified. The test can be performed in a few hours, in contrast to a period of several months required to complete the process, package the circuit and conduct a burn-in test.

Abstract: Methods for selective salicidation of a semiconductor device. The invention implements a chemical surface pretreatment by immersion in ozonated water H2O prior to metal deposition. The pretreatment forms an interfacial layer that prevents salicidation over an n-type structure. As a result, the invention does not add any additional process steps to the conventional salicidation processing.

Abstract: Disclosed is a method and structure for forming a silicide on a silicon material. The invention places the silicon material in a vacuum environment, forms metal on the silicon material, and then heats the silicon surface and the metal without breaking the vacuum environment. The processes of forming the metal and heating the silicon can be performed simultaneously without breaking the vacuum environment to form the silicide as the metal is being deposited. After the foregoing processing, the invention can remove the silicon surface from the vacuum environment and perform additional heating of the silicon surface. The first heating process forms a monosilicide and the additional heating forms a disilicide.

Abstract: The integrity of a liner in an interconnect structure or other layer in an integrate circuit is tested in a short time by exposing the liner to a reactive gas that attacks the underlying silicon or other material behind the liner. A weak spot in the liner permits the gas to react with the silicon, which produces a visible area that can be readily identified. The test can be performed in a few hours, in contrast to a period of several months required to complete the process, package the circuit and conduct a burn-in test.

Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.

Abstract: A method of preparing silicon semiconductor surfaces prior to metal silicide formation. In particular, it teaches a method of treating about 10 to about 200 Å of a surface of the silicon with a plasma source after activating the source and drain regions, prior to an HF etch and deposition of a metal for silicide formation. Discontinuities in the metal silicide formed on narrow polysilicon lines at the point where source and drain regions intersect are surprisingly diminished. This results in more continuous, uniform silicide formation hence the polysilicon lines and the source and drain regions have substantially lower resistance.