Abstract: A method of establishing a network by sharing a secret between a first entity (A) and a second entity (B), comprising the steps of: the first entity (A) broadcasting (100) an ANNOUNCE message announcing its identity and details of other entities it is aware of, wherein each of the other entities of which it is aware is associated with a particular nonce, and the message is encrypted using a broadcast encryption scheme common to the first and second entities (A,B), and; the second entity (B), upon receiving and decrypting the ANNOUNCE message, transmitting (110) to the first entity (A) a SHARE message, wherein the SHARE message comprises a signcryption of the secret, authenticated using signcryption data associated with the particular nonce associated with the second entity (B).

Abstract: A method of establishing a network by sharing a secret between a first entity (A) and a second entity (B), comprising the steps of: the first entity (A) broadcasting (100) an ANNOUNCE message announcing its identity and details of other entities it is aware of, wherein each of the other entities of which it is aware is associated with a particular nonce, and the message is encrypted using a broadcast encryption scheme common to the first and second entities (A,B), and; the second entity (B), upon receiving and decrypting the ANNOUNCE message, transmitting (110) to the first entity (A) a SHARE message, wherein the SHARE message comprises a signcryption of the secret, authenticated using signcryption data associated with the particular nonce associated with the second entity (B).

Abstract: A decoding system which is arranged to perform a plural-stage process in determining which of the driver lines to stimulate in response to each electrode address value supplied to the decoder. This enables the network configuration of the impedances to be machine generated, and also enables the decoder to calculate on the fly which driver lines to stimulate in response to each address value. Furthermore, different resolutions may be provided to enable groups of the electrodes to be addressed simultaneously. Such a decoder arrangement may also be used with an electrode arrangement in which each electrode is connected to only two of the driver lines, in order to achieve addressing schemes in which up to t consecutive electrodes can be driven simultaneously. The invention is applicable, for example, to liquid crystal displays, arrays of memory elements and arrays of sensors such as light-sensors.

Abstract: A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical defects. At manufacture, the MRAN device is tested to confirm that each set of storage cells is suitable for storing ECC encoded data, using either a parametric evaluation (step 602), or a logical evaluation (step 603) or preferably a combination of both. Failed cells are identified and a count is formed, suitably in terms of ECC symbols 206 that would be affected by such failed cells (step 604). The count can be compared to a threshold (step 605) to determine suitability of the accessed storage cells and a decision made (step 606) on whether to continue with use of those cells, or whether to take remedial action.

Abstract: A magnetoresistive solid-state storage device (MRAM device) uses storage cells 16 arranged in many arrays 10 to form a macro-array 2. For fast access times and to reduce exposure to physical failures, each unit of data (e.g. a sector) is stored with a few sub-units (e.g. bytes) in each of a large plurality of the arrays 10. Advantageously, the plurality of arrays 10 are accessible in parallel substantially simultaneously, and a failure in any one array affects only a small portion of the data unit. Optionally, error correction coding (ECC) is employed to form encoded data with symbols which are stored according to preferred embodiments which further minimise exposure to physical failures.

Abstract: A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical failures. At manufacture, the device is tested to confirm that each set of storage cells is suitable for storing ECC encoded data. The test comprises identifying failed cells where the failures will be visible in use for the generation of erasure information used in ECC decoding, by comparing parametric values obtained from the cells against one or more failure ranges, and includes performing a write-read-compare operation with test data to identify failed cells which will be hidden for the generation of erasure information in use. A failure count is formed based on both the visible failures and the hidden failures, to determine that the set of cells is suitable for storing ECC encoded data. The failure count is weighted, with hidden failures having a greater weighting than visible failures.

Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, parametric values are obtained from storage cells 16 of the device and compared to ranges to establish logical bit values, together with erasure information. The erasure information identifies symbols 206 in a block of ECC encoded data 204 which, from the parametric evaluation, are suspected to be affected by physical failures of the storage cells 16. Where the position of suspected failed symbols 206 is known from this erasure information, the ability of a decoder 22 to perform ECC decoding is substantially enhanced.

Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. ECC encoded data is read and decoded to identify failed symbols. A failure history table is then updated to indicate columns 14 of an array of storage cells 16 which are suspected to be affected by physical failures. Advantageously, erasure information is formed with reference to the failure history table, and the ability of a decoder 22 to perform ECC decoding is substantially enhanced.

Abstract: A magnetoresistive solid-state storage device (MRAM) performs error correction coding (ECC) of stored information. Since currently available MRAM devices are subject to physical failures, data storage arrangements are described to minimize the affect of those failures on the stored ECC encoded data, including storing all bits of each symbol in storage cells 16 in one row 12 (FIG. 3), or in at least two rows 12 but using storage cells 16 in the same columns 14 (FIG. 4). Sets of bits taken from each row 12 are allocated to different codewords 204 (FIG. 5) and the order of allocation can be rotated (FIG. 6). A second level of error checking can be applied by adding a parity bit 226 to each symbol 206 (FIG. 7).

Abstract: A check sum calculation on data coded with a Reed-Solomon error correcting code is performed by applying a byte based polynomial remaindering process to data bytes. The polynomial is X2+X?2+?, over GF (28), where ? is the primitive element GF (28) used to define redundancy coding for individual data groups. The roots of the polynomial used in the polynomial remaindering process differ from the roots of a generator polynomial of the Reed-Solomon error correcting code. The polynomial remaindering process is performed with a sub function mask containing the same mask function as used in defining redundancy coding for a data group or groups. The data group or groups are redundance coded using a Reed-Solomon code over GF (28).

Abstract: An electrode arrangement for an array of electrically-controllable elements has a series of generally parallel electrodes each for extending along a respective line of the electrically-controllable elements, and a series of driver lines for receiving driving signals. Each electrode is connected to a plurality of the driver lines each via a respective impedance. Each electrode is so connected to at least three of the driver lines. Additionally or alternatively, the driver lines are so connected to the electrodes such that the driver lines cannot be split into a pair of arbitrary groups of the driver lines for which (a) each group has generally the same number of driver lines and (b) each electrode is so connected to at least one of the driver lines in one of the groups and to at least one of the driver lines in the other of the groups. This enables the ratio of the number of electrodes to the number of driver lines to be increased.

Abstract: A security system based on a tamper resistant badge that becomes deactivated if the badge is removed from the person authorized to wear the badge. The badge has a volatile memory for storing the security clearance information associated with the wearer and a processor having sufficient power to perform encrypted communications. The badge also has an attachment sensor that resets the security clearance information if the badge is removed from the wearer. A secure data processing system utilizing the badges includes an administrative computer, A, and a client computer, C. Computer A has an identity verification system for authenticating the identity of individuals having badges and loading the clearance information into the volatile memory after the badge is attached to the wearer. The C computers access the information in the badge's volatile memory to provide access to the wearer at the access level specified in the volatile memory.

Abstract: A decoding system which is arranged to perform a plural-stage process in determining which of the driver lines to stimulate in response to each electrode address value supplied to the decoder. This enables the network configuration of the impedances to be machine generated, and also enables the decoder to calculate on the fly which driver lines to stimulate in response to each address value. Furthermore, different resolutions may be provided to enable groups of the electrodes to be addressed simultaneously. Such a decoder arrangement may also be used with an electrode arrangement in which each electrode is connected to only two of the driver lines, in order to achieve addressing schemes in which up to t consecutive electrodes can be driven simultaneously. The invention is applicable, for example, to liquid crystal displays, arrays of memory elements and arrays of sensors such as light-sensors.

Abstract: A magnetoresistive solid-state storage device (MRAM) performs error correction coding (ECC) of stored information. At manufacture or during use, each logical block of ECC encoded data and/or the corresponding set of storage cells are evaluated to determine suitability for continued use, or whether remedial action is necessary. In a first preferred method ECC decoding is attempted to determine whether information is unrecoverable from the block of ECC encoded data. In a second preferred method a parametric evaluation is made prior to attempting ECC decoding.

Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. ECC encoded data is read and decoded to identify failed symbols. A failure history table is then updated to indicate columns 14 of an array of storage cells 16 which are suspected to be affected by physical failures. Advantageously, erasure information is formed with reference to the failure history table, and the ability of a decoder 22 to perform ECC decoding is substantially enhanced.

Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, parametric values are obtained from storage cells 16 of the device and compared to ranges to establish logical bit values, together with erasure information. The erasure information identifies symbols 206 in a block of ECC encoded data 204 which, from the parametric evaluation, are suspected to be affected by physical failures of the storage cells 16. Where the position of suspected failed symbols 206 is known from this erasure information, the ability of a decoder 22 to perform ECC decoding is substantially enhanced.

Abstract: A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical defects. At manufacture, the MRAM device is tested to confirm that each set of storage cells is suitable for storing ECC encoded data, using either a parametric evaluation (step 602), or a logical evaluation (step 603) or preferably a combination of both. Failed cells are identified and a count is formed, suitably in terms of ECC symbols 206 that would be affected by such failed cells (step 604). The count can be compared to a threshold (step 605) to determine suitability of the accessed storage cells and a decision made (step 606) on whether to continue with use of those cells, or whether to take remedial action.

Abstract: A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical failures. At manufacture, the MRAM device is tested to confirm that each set of storage cells is suitable for storing ECC encoded data. The test comprises identifying failed storage cells where the failures will be visible in use for the generation of erasure information used in ECC decoding, suitably by comparing parametric values obtained from the storage cells against one or more failure ranges, and includes performing a write-read-compare operation with test data to identify failed storage cells which will be hidden for the generation of erasure information in use. A failure count is formed based on both the visible failures and the hidden failures, to determine that the set of storage cells is suitable for storing ECC encoded data. Here, the failure count is weighted, with hidden failures having a greater weighting than visible failures.

Abstract: A magnetoresistive solid-state storage device (MRAM device) uses storage cells 16 arranged in many arrays 10 to form a macro-array 2. For fast access times and to reduce exposure to physical failures, each unit of data (e.g. a sector) is stored with a few sub-units (e.g. bytes) in each of a large plurality of the arrays 10. Advantageously, the plurality of arrays 10 are accessible in parallel substantially simultaneously, and a failure in any one array affects only a small portion of the data unit. Optionally, error correction coding (ECC) is employed to form encoded data with symbols which are stored according to preferred embodiments which further minimise exposure to physical failures.

Abstract: A magnetoresistive solid-state storage device (MRAM) performs error correction coding (ECC) of stored information. Since currently available MRAM devices are subject to physical failures, data storage arrangements are described to minimise the affect of those failures on the stored ECC encoded data, including storing all bits of each symbol in storage cells 16 in one row 12 (FIG. 3), or in at least two rows 12 but using storage cells 16 in the same columns 14 (FIG. 4). Sets of bits taken from each row 12 are allocated to different codewords 204 (FIG. 5) and the order of allocation can be rotated (FIG. 6). A second level of error checking can be applied by adding a parity bit 226 to each symbol 206 (FIG. 7).