Abstract: A directory memory system including a plurality of reconfigurable subarrays of memory cells and having the capability of simultaneously performing write/compare, read/compare, compare/bypass, write/bypass, or write/compare/bypass operations. The present system may be fabricated on a single integrated circuit chip and includes circuitry for selectively writing data into the subarrays. Output data from the subarrays is connected to compare data logic for comparing the subarray data to one or more bytes of compare input data, and to bit select logic for selectively placing the subarray data onto an output bus. Bypass select logic causes either the subarray data or one byte of compare data to be output from the memory system data output port. In one embodiment, two bytes of compare input data can be simultaneously compared with a selected data byte from each of the subarrays, and one byte of compare input data can be bypassed to the data output port during the compare operation.