Abstract: In some examples, a controller is configured to generate a key based on a physics-based output of a component. The controller may, for example, use the key to authenticate communication between at least two nodes, to encrypt data, or to decrypt data, may be generated based on a physics-based output generated a component. The output generated by the component may vary over time, such that the controller is configured to generate a different key, depending on the time at which the output from the component used to generate the key was generated by the component. In some examples, the key is not stored in a memory, and is a discrete signal that only exists in real-time while the component is active and generating the detectable output.

Abstract: In some examples, an integrated circuit system includes a plurality of integrated circuit layers. At least one of the integrated circuit layers includes an integrated circuit die, which may not include any through-silicon vias that provide a pathway to an adjacent integrated circuit layer, and an interposer portion, which includes electrically conductive through-vias. The interposer portion may facilitate communication of the integrated circuit die with other integrated circuit layers of the integrated circuit system. In some examples, the stacked integrated circuit system may include more than one integrated circuit die, which may be in the same integrated circuit layer as at least one other integrated circuit die, or may be in a different integrated circuit layer.

Abstract: In some examples, a controller is configured to generate a key based on a physics-based output of a component. The controller may, for example, use the key to authenticate communication between at least two nodes, to encrypt data, or to decrypt data. In some examples, the component includes one or more subcomponents, each subcomponent including a cell filled with a gas, a light source configured to transmit a light through the gas cell, and a photodetector configured to sense light transmitted through the gas cell. The photodetector of each subcomponent is configured to generate an electrical signal that changes as a function of one or more properties of the light sourced by the light source, transmitted through the gas cell. The output of the component can is based on the signals generate by the one or more photodetectors.

Abstract: Systems and methods for a wafer scale atomic clock are provided. In at least one embodiment, a wafer scale device comprises a first substrate; a cell layer joined to the first substrate, the cell layer comprising a plurality of hermetically isolated cells, wherein separate measurements are produced for each cell in the plurality of hermetically isolated cells; and a second substrate joined to the cell layer, wherein the first substrate and the second substrate comprise electronics to control the separate measurements, wherein the separate measurements are combined into a single measurement.

Abstract: In some examples, a controller is configured to generate a key based on a physics-based output of a component. The controller may, for example, use the key to authenticate communication between at least two nodes, to encrypt data, or to decrypt data, may be generated based on a physics-based output generated a component. The output generated by the component may vary over time, such that the controller is configured to generate a different key, depending on the time at which the output from the component used to generate the key was generated by the component. In some examples, the key is not stored in a memory, and is a discrete signal that only exists in real-time while the component is active and generating the detectable output.

Abstract: In some examples, a controller is configured to generate a key based on a physics-based output of a component. The controller may, for example, use the key to authenticate communication between at least two nodes, to encrypt data, or to decrypt data. In some examples, the component includes one or more subcomponents, each subcomponent including a cell filled with a gas, a light source configured to transmit a light through the gas cell, and a photodetector configured to sense light transmitted through the gas cell. The photodetector of each subcomponent is configured to generate an electrical signal that changes as a function of one or more properties of the light sourced by the light source, transmitted through the gas cell. The output of the component can is based on the signals generate by the one or more photodetectors.

Abstract: Systems and methods for a wafer scale atomic clock are provided. In at least one embodiment, a wafer scale device comprises a first substrate; a cell layer joined to the first substrate, the cell layer comprising a plurality of hermetically isolated cells, wherein separate measurements are produced for each cell in the plurality of hermetically isolated cells; and a second substrate joined to the cell layer, wherein the first substrate and the second substrate comprise electronics to control the separate measurements, wherein the separate measurements are combined into a single measurement.

Abstract: An integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and connections. The bond coat layer is configured to encapsulate the IC components. The top coat layer has at least a portion embedded in the bond coat layer. Moreover, the top coat layer includes a fibrous interface configured to provide security and strengthen the bond coat layer.

Abstract: An integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and connections. The bond coat layer is configured to encapsulate the IC components. The top coat layer has at least a portion embedded in the bond coat layer. Moreover, the top coat layer includes a fibrous interface configured to provide security and strengthen the bond coat layer.

Abstract: An integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and connections. The bond coat layer is configured to encapsulate the IC components. The top coat layer has at least a portion embedded in the bond coat layer. Moreover, the top coat layer includes a fibrous interface configured to provide security and strengthen the bond coat layer.

Abstract: In some examples, an integrated circuit system includes a plurality of integrated circuit layers. At least one of the integrated circuit layers includes an integrated circuit die, which may not include any through-silicon vias that provide a pathway to an adjacent integrated circuit layer, and an interposer portion, which includes electrically conductive through-vias. The interposer portion may facilitate communication of the integrated circuit die with other integrated circuit layers of the integrated circuit system. In some examples, the stacked integrated circuit system may include more than one integrated circuit die, which may be in the same integrated circuit layer as at least one other integrated circuit die, or may be in a different integrated circuit layer.

Abstract: A security coating on an electronic circuit assembly comprises a mesh coating that may have a unique signature pattern and comprise materials that easily produce an image of the signature so that it is possible to determine if reverse engineering has been attempted. Spaces in the mesh may include electrical components to erase circuit codes to destroy the functionality and value of the protected die if the mesh coated is disturbed. The voids may include compositions to enhance the mesh signature and abrade the circuit if tampering takes place.

Abstract: A security coating on an electronic circuit assembly comprises a mesh coating that may have a unique signature pattern and comprise materials that easily produce an image of the signature so that it is possible to determine if reverse engineering has been attempted. Spaces in the mesh may include electrical components to erase circuit codes to destroy the functionality and value of the protected die if the mesh coated is disturbed. The voids may include compositions to enhance the mesh signature and abrade the circuit if tampering takes place.

Abstract: A secure connector is provided. The secure connector comprises a casing; a tamper sensor disposed inside the casing and configured to detect unauthorized tamper events; and one or more conductors configured to carry signals, the one or more conductors passing through the tamper sensor.

Abstract: A security coating on an electronic circuit assembly comprises a mesh coating that may have a unique signature pattern and comprise materials that easily produce an image of the signature so that it is possible to determine if reverse engineering has been attempted. Spaces in the mesh may include electrical components to erase circuit codes to destroy the functionality and value of the protected die if the mesh coated is disturbed. The voids may include compositions to enhance the mesh signature and abrade the circuit if tampering takes place.

Abstract: An anti-tamper system is provided. The anti-tamper system comprises a clamshell protective encasement adapted to encapsulate at least one device on a single circuit board such that at least one electrical connector of the single circuit board is accessible. The anti-tamper system also comprises one or more sensors embedded inside the clamshell protective encasement, the one or more sensors being adapted to detect unauthorized attempts to tamper with the clamshell protective encasement.

Abstract: A fiber optic sensor coil and method of forming a fiber optic sensor coil including a plurality of turns of a first segment of optical fiber wound in a clockwise direction and a plurality of turns of a second segment of optical fiber wound in the counterclockwise direction. The turns of the first segment and of the second segment together forming a plurality of layers of turns of the optical fiber. A restraining ring covers an outermost layer of the plurality of layers of turns of optical fiber. The restraining ring includes a plurality of openings formed therein and provides a compressive force to the plurality of turns of the optical fiber.

Abstract: An improved system and method for protecting sensitive electronic equipment or components against unauthorized access, by detecting and also reacting to unauthorized intrusions into the enclosures for the sensitive electronic equipment or components is disclosed. For example, a protective system for protecting sensitive electronic equipment or components against unauthorized access is disclosed that includes a fiber optic cable mesh or network attached to, or embedded in, the walls of the enclosure for the electronic equipment or components. A continuous signal or burst is applied to the fiber optic cable, which is coupled to an optical signal detection device. Thus, any attempt to remove or penetrate the walls of the enclosure interrupts the signal in the fiber optic cable, and the interruption of the signal is detected by the optical signal detection device.

Abstract: an integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and connections. The bond coat layer is configured to encapsulate the IC components. The top coat layer has at least a portion embedded in the bond coat layer. Moreover, the top coat layer includes a fibrous interface configured to provide security and strengthen the bond coat layer.

Abstract: A secure chassis comprises a plurality of walls, wherein each wall comprises an inner portion; an outer portion; and a tamper sensor disposed between the inner portion and the outer portion of each wall, the tamper sensor configured to detect unauthorized tamper events; wherein the plurality of walls are coupled together to form an enclosure to house one or more components.