Abstract: Systems and methods for codependent physical unclonable function (PUF)/random number generator (RNG) generator pairing for physical provenance are described herein. In one example a device includes physical unclonable function (PUF) circuitry configured to produce a PUF output in response to an input and random number generator (RNG) circuitry configured to output one or more random numbers. The PUF circuitry and the RNG circuitry share one or more components such that an alteration of the RNG circuitry alters the PUF circuitry. The device is configured to determine whether the RNG circuitry is an untainted source of random numbers based on an output of the PUF circuitry.

Abstract: A system is provided. The system includes a physical unclonable function (PUF) circuit having an input, an output and an embedded microelectromechanical system (MEMS) device; and an interface, coupled to the PUF circuit, and being configured to be coupled to a mechanical structure; wherein the embedded MEMS device is configured to detect a parameter or characteristic associated with the mechanical structure and to provide an input to the PUF circuit based on the detected parameter, whereby the PUF circuit uses the input from the embedded MEMS device to extend trust to the mechanical structure.

Abstract: A system that includes: a microelectromechanical system (MEMS) device for generating an output signal at an output of the MEMS device, the MEMS device receiving at least one input signal at an input of the MEMS device; a storage medium configured to store a signal injection function and an output generation function; and a processor, in communication with the MEMS device and the storage medium, the processor configured to run the signal injection function to selectively modify the at least one input signal to produce a modified input signal and to provide the modified input signal to the input of the MEMS device, and that is configured to run an output generation function to extract a random component and a unique component from the output signal, wherein the random component and the unique component are generated by the MEMS device based on the modified at least one input signal.

Abstract: In some examples, a controller is configured to generate a key based on a physics-based output of a component. The controller may, for example, use the key to authenticate communication between at least two nodes, to encrypt data, or to decrypt data, may be generated based on a physics-based output generated a component. The output generated by the component may vary over time, such that the controller is configured to generate a different key, depending on the time at which the output from the component used to generate the key was generated by the component. In some examples, the key is not stored in a memory, and is a discrete signal that only exists in real-time while the component is active and generating the detectable output.

Abstract: In some examples, an integrated circuit system includes a plurality of integrated circuit layers. At least one of the integrated circuit layers includes an integrated circuit die, which may not include any through-silicon vias that provide a pathway to an adjacent integrated circuit layer, and an interposer portion, which includes electrically conductive through-vias. The interposer portion may facilitate communication of the integrated circuit die with other integrated circuit layers of the integrated circuit system. In some examples, the stacked integrated circuit system may include more than one integrated circuit die, which may be in the same integrated circuit layer as at least one other integrated circuit die, or may be in a different integrated circuit layer.

Abstract: In some examples, a controller is configured to generate a key based on a physics-based output of a component. The controller may, for example, use the key to authenticate communication between at least two nodes, to encrypt data, or to decrypt data. In some examples, the component includes one or more subcomponents, each subcomponent including a cell filled with a gas, a light source configured to transmit a light through the gas cell, and a photodetector configured to sense light transmitted through the gas cell. The photodetector of each subcomponent is configured to generate an electrical signal that changes as a function of one or more properties of the light sourced by the light source, transmitted through the gas cell. The output of the component can is based on the signals generate by the one or more photodetectors.

Abstract: Systems and methods for a wafer scale atomic clock are provided. In at least one embodiment, a wafer scale device comprises a first substrate; a cell layer joined to the first substrate, the cell layer comprising a plurality of hermetically isolated cells, wherein separate measurements are produced for each cell in the plurality of hermetically isolated cells; and a second substrate joined to the cell layer, wherein the first substrate and the second substrate comprise electronics to control the separate measurements, wherein the separate measurements are combined into a single measurement.

Abstract: In some examples, a controller is configured to generate a key based on a physics-based output of a component. The controller may, for example, use the key to authenticate communication between at least two nodes, to encrypt data, or to decrypt data, may be generated based on a physics-based output generated a component. The output generated by the component may vary over time, such that the controller is configured to generate a different key, depending on the time at which the output from the component used to generate the key was generated by the component. In some examples, the key is not stored in a memory, and is a discrete signal that only exists in real-time while the component is active and generating the detectable output.

Abstract: In some examples, a controller is configured to generate a key based on a physics-based output of a component. The controller may, for example, use the key to authenticate communication between at least two nodes, to encrypt data, or to decrypt data. In some examples, the component includes one or more subcomponents, each subcomponent including a cell filled with a gas, a light source configured to transmit a light through the gas cell, and a photodetector configured to sense light transmitted through the gas cell. The photodetector of each subcomponent is configured to generate an electrical signal that changes as a function of one or more properties of the light sourced by the light source, transmitted through the gas cell. The output of the component can is based on the signals generate by the one or more photodetectors.

Abstract: Systems and methods for a wafer scale atomic clock are provided. In at least one embodiment, a wafer scale device comprises a first substrate; a cell layer joined to the first substrate, the cell layer comprising a plurality of hermetically isolated cells, wherein separate measurements are produced for each cell in the plurality of hermetically isolated cells; and a second substrate joined to the cell layer, wherein the first substrate and the second substrate comprise electronics to control the separate measurements, wherein the separate measurements are combined into a single measurement.

Abstract: An integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and connections. The bond coat layer is configured to encapsulate the IC components. The top coat layer has at least a portion embedded in the bond coat layer. Moreover, the top coat layer includes a fibrous interface configured to provide security and strengthen the bond coat layer.

Abstract: An integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and connections. The bond coat layer is configured to encapsulate the IC components. The top coat layer has at least a portion embedded in the bond coat layer. Moreover, the top coat layer includes a fibrous interface configured to provide security and strengthen the bond coat layer.

Abstract: An integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and connections. The bond coat layer is configured to encapsulate the IC components. The top coat layer has at least a portion embedded in the bond coat layer. Moreover, the top coat layer includes a fibrous interface configured to provide security and strengthen the bond coat layer.

Abstract: In some examples, an integrated circuit system includes a plurality of integrated circuit layers. At least one of the integrated circuit layers includes an integrated circuit die, which may not include any through-silicon vias that provide a pathway to an adjacent integrated circuit layer, and an interposer portion, which includes electrically conductive through-vias. The interposer portion may facilitate communication of the integrated circuit die with other integrated circuit layers of the integrated circuit system. In some examples, the stacked integrated circuit system may include more than one integrated circuit die, which may be in the same integrated circuit layer as at least one other integrated circuit die, or may be in a different integrated circuit layer.

Abstract: A security coating on an electronic circuit assembly comprises a mesh coating that may have a unique signature pattern and comprise materials that easily produce an image of the signature so that it is possible to determine if reverse engineering has been attempted. Spaces in the mesh may include electrical components to erase circuit codes to destroy the functionality and value of the protected die if the mesh coated is disturbed. The voids may include compositions to enhance the mesh signature and abrade the circuit if tampering takes place.

Abstract: A security coating on an electronic circuit assembly comprises a mesh coating that may have a unique signature pattern and comprise materials that easily produce an image of the signature so that it is possible to determine if reverse engineering has been attempted. Spaces in the mesh may include electrical components to erase circuit codes to destroy the functionality and value of the protected die if the mesh coated is disturbed. The voids may include compositions to enhance the mesh signature and abrade the circuit if tampering takes place.

Abstract: A secure connector is provided. The secure connector comprises a casing; a tamper sensor disposed inside the casing and configured to detect unauthorized tamper events; and one or more conductors configured to carry signals, the one or more conductors passing through the tamper sensor.

Abstract: A security coating on an electronic circuit assembly comprises a mesh coating that may have a unique signature pattern and comprise materials that easily produce an image of the signature so that it is possible to determine if reverse engineering has been attempted. Spaces in the mesh may include electrical components to erase circuit codes to destroy the functionality and value of the protected die if the mesh coated is disturbed. The voids may include compositions to enhance the mesh signature and abrade the circuit if tampering takes place.

Abstract: An anti-tamper system is provided. The anti-tamper system comprises a clamshell protective encasement adapted to encapsulate at least one device on a single circuit board such that at least one electrical connector of the single circuit board is accessible. The anti-tamper system also comprises one or more sensors embedded inside the clamshell protective encasement, the one or more sensors being adapted to detect unauthorized attempts to tamper with the clamshell protective encasement.

Abstract: A fiber optic sensor coil and method of forming a fiber optic sensor coil including a plurality of turns of a first segment of optical fiber wound in a clockwise direction and a plurality of turns of a second segment of optical fiber wound in the counterclockwise direction. The turns of the first segment and of the second segment together forming a plurality of layers of turns of the optical fiber. A restraining ring covers an outermost layer of the plurality of layers of turns of optical fiber. The restraining ring includes a plurality of openings formed therein and provides a compressive force to the plurality of turns of the optical fiber.